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2020-09-09Make a couple variables static.staticTim Newsome2-4/+2
2020-09-03Fix usage for our RISC-V commands. (#521)Tim Newsome2-24/+20
Change-Id: Ia4e020637aae2384af223b0210ef2aef6a14b31a
2020-09-03Check malloc/calloc return values. (#517)Tim Newsome4-9/+96
Should not affect anything, but requested in http://openocd.zylin.com/#/c/5821/5/src/target/riscv/batch.c@28 Change-Id: Ib7185bd93eeb918e72872416ab6364f8776cff88
2020-09-01user4 0x23 should be MSB. (#519)Jiuyang Liu1-1/+7
Signed-off-by: Jiuyang Liu <jiuyang.liu@sifive.com>
2020-08-31Make checkpatch require Signed-off-by (#516)Tim Newsome2-3/+3
* Make checkpatch require Signed-off-by This will make it easier to send changes contributed here to mainline OpenOCD. (Intentionally not including the required line here to make sure I can't just merge this.) Change-Id: I089084d38f3e08859d62cf7eface405f37af4799 * Whitespace fix. This PR isn't building on travis. Maybe because I only changed .travis.yml. Here's a source change to force a build (hopefully). Change-Id: I8a828fe1d56a1960bc4bfb91d3d2f3a0790ad571 * Can't check for signoff on sources alone. Change-Id: I741a299b64bf14857a4e1807b254a7d270b2e466 Signed-off-by: Tim Newsome <tim@sifive.com> * Actual whitespace fixes. Why didn't this fail to build before? Change-Id: I339c03c4ef96546dbef5f16e635921a4fdaf9b35 Signed-off-by: Tim Newsome <tim@sifive.com>
2020-08-24Add SPDX tags for RISC-V files. (#513)Tim Newsome12-0/+24
Requested in http://openocd.zylin.com/#/c/5821/3 Change-Id: I95551a3311d8e128300bacdf463da7ab4edf29a0
2020-08-24Update encoding.h from riscv-opcodes (#514)Tim Newsome5-256/+583
Rename dscratch to dscratch0, since that is what it's called in the spec. Change-Id: Id6271ae272e979cef69e8ef0577b23452fb84f51
2020-08-24Update debug_defines.h from riscv-debug-spec (#515)Tim Newsome3-1700/+1783
A ton of constants got a new prefix, so I made a lot of changes to match, but no functional changes. I did define DTM_DMI_MAX_ADDRESS_LENGTH in batch.c. That definition never should have been in debug_defines.h, which I missed during code review. Change-Id: If5d86660f84bb0a3f2865fb36ef05d6630486d8b
2020-08-21Mostly whitespace changes. (#511)Tim Newsome4-35/+35
Requested in http://openocd.zylin.com/#/c/5821/3 Change-Id: I75e6d551091396fc6e81b3642ae44bafe358eed7
2020-08-18Update to version 1.0 of the vector spec. (#505)Tim Newsome1-1/+1
Accessing registers on targets that implement 0.9 or earlier will no longer work. If you need that we can talk about making it a config option. Change-Id: I953b639cf9a92ee9b0422e035da57c1d07504237
2020-08-18Create `riscv repeat_read` command (#510)Tim Newsome7-85/+180
* WIP, apply stash with conflicts. Change-Id: Ia794bde419aa29161c68898d20e30527e69f5a31 * Fix conflict resolution problems. Change-Id: I4cedc348cf613f98cc5a36886f37c568ca644238 * Add repeat_read command. Only implemented for sba v1 right now, and poorly tested at that. Change-Id: I1d9ff63e1dea14b3f6a9f8ba4dad53668bf8038b * Hide bogus address in repeat_read Change-Id: Ib66c1fa60df9c7fc7cc87880b0fddc52825b48aa * WIP make repeat read work with progbuf. Change-Id: I555f8b880c8bf0d1ed0f3f90c7987a5b516a7a79 * WIP Change-Id: Ic567cea68355ae907e94bd25185a2c9be6fd798d * Fix error handling when increment is non-zero. Change-Id: I5a2f3f2ee948fd4e12c0443a542e85b7b5c5791a * Correctly(?) handle failures when increment is 0. I'm not 100% convinced that this ensures every read value shows up in the output, but it ought to work. Change-Id: I1af3e7174cf9d5e6f293456fb5ead629e17faaaa * Don't crash when asked to read no data. Change-Id: I4061b5c720a43a4f828384ab9eacc89557adfa05 * Remove unnecessary comment. Change-Id: I1be3d699b86299339b3a830ca1ef13c9f5b9fe0f * Document `riscv repeat_read`. Change-Id: I4a0f071f38784b2de034f8c1b0ce75d6d2d326b2
2020-08-17Account for impebreak in size requirements for progbuf (#509)Samuel Obuch1-30/+26
* Account for impebreak in size requirements for progbuf * add helper function
2020-08-07Fix of DMI batch scans over 64-bits (#432)Jan Matyas4-27/+37
This fixes buffer overrun/data corruption during DMI scan batches on targets with large value of dtmcs.abits > 30 (unusual, but within the spec).
2020-07-17Further deprecate `-rtos riscv`. (#499)Tim Newsome1-0/+19
* Further deprecate `-rtos riscv`. Now using `-rtos riscv` will result in a failure, which you can (until the end of this year) bypass by adding `enable_rtos_riscv` to the configuration. Change-Id: Ic714c303dc1b00c19e8956609730c0f83c845cb6 * Make checkpatch happy. Change-Id: I0469ec37d38ad2eadf25efb5b2b7ac88391c0f51
2020-07-07Triggers with type=0 aren't real. (#496)Tim Newsome1-1/+5
Fixes #491. Change-Id: Id01adcc68d8c7d95f7e86d49d5d2b0c97c9fb1b0
2020-07-02Merge pull request #494 from riscv/from_upstreamTim Newsome79-683/+8859
Get changes from upstream
2020-07-01Warn if we are asked to read/write 0 bytes. (#492)Tim Newsome1-0/+10
Technically that might be OK, but in practice it probably indicates something went wrong somewhere. Before this change OpenOCD would crash if it happened. Change-Id: I2500ba67ec282915dcf2b2488f2aac9fbfdb23a3
2020-06-30Merge branch 'riscv' into from_upstreamTim Newsome2-6/+6
Change-Id: Ia9c5d7c7f0a4913c1af17e042266736943334c7f
2020-06-25Don't halt the algorith-running hart because another is halted. (#490)Tim Newsome1-3/+1
This logic is a little tortured, but it still passes the semihosting tests that were the cause for the recent rewrite. Change-Id: Ic6760bb068621ab2a49feb0cf3998fc6957b5cfc
2020-06-25Accept dmstatus.version==3 (0.14) (#489)Tim Newsome1-3/+5
Fixes #485. Change-Id: I60b3d68827ca726558bc28035c0b74c5cf0d9754
2020-06-23Merge branch 'master' into from_upstreamTim Newsome79-683/+8859
Conflicts: .gitmodules .travis.yml jimtcl src/jtag/core.c src/jtag/drivers/ftdi.c src/jtag/drivers/libjaylink src/jtag/drivers/mpsse.c src/jtag/drivers/stlink_usb.c src/rtos/hwthread.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c tcl/board/sifive-hifive1-revb.cfg Change-Id: I2d26ebeffb4c1374730d2e20e6e2a7710403657c
2020-06-18Step/resume off manual hardware triggers (#486)Tim Newsome2-30/+119
* Accommodate users setting custom triggers. RISC-V hardware supports many more triggers than gdb can communicate to OpenOCD. Accommodate users that set triggers by writing tdata* directly, by disable/step/reenable when a user has done that. Note that users must set dmode in tdata1 for this behavior to work properly. Triggers with dmode=0 are assumed to be set and handled by the software that is being debugged. Change-Id: Ib0751689c5553aae3a273395b10f5b98326fa066 * Enumerate triggers when resuming from a trigger Otherwise when we connect to a target that's already halted due to a trigger, we won't correctly step past it. Change-Id: I23b9482fa9597af826770f9cebf247b7ba59f65c * Also disable/reenable triggers around single step. Gdb is smart enough to disable/step/resume if it set the triggers, but if a user set them manually it also needs to happen. Change-Id: I1251bd47199b6f15f61a93e3a521a53f2b677c5f * Fix whitespace. Change-Id: Icc240aecbc7e3e36ce4e4d784f5703304334ca13
2020-06-18target/armv7m_trace: Calculate prescaler for external capture devicesMarc Schink1-0/+16
This fixes a regression introduced in "2dc88e1479f29ef0141b05bfcd907ad9a3e2d54c" Change-Id: I04dc19ed30118a4c499b83732700b2ee0fdb67b6 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5610 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-06-16riscv: Avoid shadowing read_csr/write_csr macros (#483)Khem Raj1-6/+6
The name conflict is picked by compiler and it fails to compile for rv64 Fixes src/target/riscv/riscv-011.c:1014:44: error: too many arguments provided to function-like macro invocation static int read_csr(struct target *target, uint64_t *value, uint32_t csr) ^ Signed-off-by: Khem Raj <raj.khem@gmail.com>
2020-06-06coding style: fix multi-line dereferencingAntonio Borneo1-2/+2
Issue identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types MULTILINE_DEREFERENCE -f {} \; Change-Id: Icba05613e22a72ecc3e6a0aad7cb6b479496146f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5629 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de>
2020-06-06target/cortex_a: fix memory leak of register cacheAntonio Borneo4-0/+25
There is no method to free the register cache, allocated in armv4_5, so we get a memory leak. Issue identified by valgrind. Implement the method arm_free_reg_cache() and call it in cortex_a deinit and to exit for error during arm_dpm_setup(). Tested on dual cortex-A stm32mp15x. This change is inspired from similar fix in commit b01b5fe13a67 ("armv7m: Fix memory leak in register caching."). The same allocation is also used by target types "arm7tdmi", "arm9tdmi", "arm11" and "xscale" but they all lack the deinit method and I do not have relevant HW to test the fix. For such reasons they are not addressed in this patch. Change-Id: I4da1e1f12e36ec245d1f3b11a4eafcbd9a1d2e25 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5693 Tested-by: jenkins
2020-06-06target/mem_ap: fix two memory leaksAntonio Borneo1-0/+10
The target mem_ap misses the method 'deinit_target' and does not free the memory allocated during 'target create' and 'configure'. Add the missing method and free the allocated memory. Issue identified with valgrind. Change-Id: If0d0114a75dd76a8b65c2d46d96c6085fd31a09d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5700 Tested-by: jenkins
2020-06-06target/cortex-m: enable C_DEBUGEN during examineAntonio Borneo1-0/+13
Current code for Cortex M does not set C_DEBUGEN as soon as possible, (which means during target examine), but later-on either: 1) at command 'halt' (e.g. for 'gdb-attach' event); 2) at command 'soft_reset_halt'; 3) at commands 'reset', 'reset halt' or 'reset init'; 4) during polling, but only if the target: = enter in 'double fault', or = exit from a reset, or = halts (not possible if C_DEBUGEN is not set) Plus, if commands in 1) or 2) are executed before the very first poll of the target, the value of 'cortex_m->dcb_dhcsr' is used not initialized while writing it back in DCB_DHCSR. Another side effect of this situation is that it's possible to set a HW breakpoint with the target running, while C_DEBUGEN is not set. Accordingly to [1], C1.3.1 "Debug authentication": When DGBEN is LOW and DHCSR.S_HALT == 0: ... FPB breakpoints do not generate an entry to Debug state and, if no DebugMonitor exception is generated, will escalate to HardFault, Lockup, or be ignored. On STM32MP15x I get HW breakpoint ignored, while on STM32F411 I get HardFault. E.g. following these steps: - power-on a pre-flashed board that starts running the firmware; - connect openocd, without halting or resetting the board; - set a HW breakpoint to some address often executed; - wait, but the board doesn't halt ...; - type the command 'halt'; - if the Cortex-M has HardFault it would be visible and the fault is at the breakpoint address; - if no HardFault then type the command 'resume'; - wait and the board will finally halt at the HW breakpoint. A similar issue has been detected on Cortex-A code and fixed by commit bff87a7f28fb ("target/cortex_a: enable DSCR_HALT_DBG_MODE during examine"). Follow the same approach and set C_DEBUGEN during examine. Also, initialize 'cortex_m->dcb_dhcsr' during examine. [1] ARM DDI 0403E "ARM v7-M Architecture Reference Manual" Change-Id: I5b0b23403634f7dfce38f104bba9f59c33eb3e99 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5702 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Moritz Fischer <moritzf@google.com>
2020-06-06arm_adi_v5: dap_ti_be_32_quirks_command minor simplificationTarek BOCHKATI1-18/+2
use handle_command_parse_bool within dap_ti_be_32_quirks_command to make it shorter and simpler. Change-Id: Ice179cc477933b27e27235dc2ade23fe655e233d Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5708 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-06arm_adi_v5: enhance command error reportingTarek BOCHKATI1-17/+32
avoid the usage of ERROR_COMMAND_SYNTAX_ERROR when ERROR_COMMAND_ARGUMENT_INVALID is more adequate. Change-Id: Ic9aaedb93fedd45efee1b39f8ea20185f01af2da Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5654 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-26Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issu… (#479)Tommy Murphy1-3/+22
* Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issues/474 * Updated code based on feedback from @timsifive
2020-05-24openocd: properly use jim data typesAntonio Borneo2-3/+4
The jim library exports all the data types through typedef, so there is no need to use the internal struct types. Fix the few remaining inconsistencies in the code. Change-Id: Id4ae0083563ea7a371833374e7b39f17158f66a4 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5662 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-05-24stm8 target: make adapter speed settings workAke Rehnman1-11/+29
Previously the adapter speed settings were hard-coded to connect with low speed then switch over to high speed regardless what was mentioned in the cfg files. Now the stm8 target intercept adapter speed settings and configure the stm8 control registers accordingly. Change-Id: I7419514e5214e4b43b9d51253cf5b7f04a233533 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/5548 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-24swim: fix adapter speed handlingAntonio Borneo1-1/+1
SWIM transport only supports two adapter speeds: - "low speed" equal to 363 kHz (8 MHz / 22) - "high speed" equal to 800 kHz (8 MHz / 10) Replace the previous convention that use "0" or "1" for "low" or "high" speed with the effective speed in kHz. Rework the implementation of stlink_speed_swim(). Set low speed in the stm8 config files, because only low speed is permitted at debug connection; the previous code ignores the initial value. Change-Id: I2484c9419a2c554c59eb6b9216339393ab0b54f3 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5529 Tested-by: jenkins
2020-05-24swim: abstract the transport in stm8 targetAntonio Borneo1-53/+16
SWIM is implemented by (ab)using the HLA API. This was acceptable when OpenOCD code did not provided a clear separation between transports and related APIs. Still today SWIM in OpenOCD is only supported by STLink, so the decision to re-use the HLA API was the simpler way to implement it. After commit efd1d642220a ("adapter: switch from struct jtag_interface to adapter_driver") the transports API are better split and SWIM can be implemented as a separate set of API. This would open the possibility to extend OpenOCD for other adapters that provide SWIM, e.g. versaloon, or through SPI emulation [1]. Introduce a new set of files swim.[ch] to handle the SWIM API. Beside the API that almost match the transport low-level data communication (system_reset, read_mem, write_mem), add a further API reconnect. Today, inside HLA STLink code, the reconnect is implemented by hacking the HLA API state(). Please notice that due to this hack the return type is incorrect; stlink_usb_state() returns ERROR_OK in SWIM mode, while its return type is enum target_state. Ignore the type mismatch and still call the HLA API state in the new SWIM API reconnect. Further commit will fix it. [1] http://kuku.eu.org/?projects/stm8spi/stm8spi Change-Id: I52018e1e2200cbd41af8e5031f7b35dc761b61d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5528 Tested-by: jenkins
2020-05-24arm_disassembler: fix typo 'ARM_UNKNOWN_INSTUCTION' to '.._INSTRUCTION'Tarek BOCHKATI2-2/+2
Change-Id: I3a3d566fe96fb1497cf8337389e993e0f728a64b Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5657 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-19Fix semihosting for multicore targets (#478)Tim Newsome4-75/+131
* WIP making semihosting work with -rtos hwthread. Change-Id: Icb46f3eeedc1391e8fdc73c3ad8036f20267eb2e * More WIP. Change-Id: I670a6e1ba2a13a6ef2ae303a99559a16fdd1bbfb * Fix halting due to a trigger. Change-Id: Ie7caa8dde9518bcd5440e34cf31ed0d30ebf29ad * Fix multicore semihosting without halt groups. Change-Id: I53587e5234308ed2cc30a7132c86e4c94eb176c4 * WIP Change-Id: I40630543b08d8b533726cb3f63aa60a62be8ef40 * Fix single core semihosting. This was the last bug! Change-Id: I593abac027fa9707f48b7f58163d7089574a0e28 * Fix whitespace. Change-Id: I285c152970b87864c63803fae61312e5b79dfe6d
2020-05-18Speed up SBA block reads roughly 2x. (#477)Tim Newsome1-3/+49
* Speed up SBA block reads roughly 2x. Change-Id: I4e4f5530d4abae7470fd00308361e727904367d2 * Fix whitespace. Change-Id: I28a1269c489d051560a2455973f9a8574f35f487
2020-05-14target/arc: fix build with clangAntonio Borneo1-1/+1
Commit da41bce3aee9 ("target/arc: introduce breakpoint functionality") introduces a mismatch between the format string and one int constant. Change the format string to match the int constant. Change-Id: I0d59552205551b90e165c0a2e3fef247ad0c7701 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: da41bce3aee9 ("target/arc: introduce breakpoint functionality") Reviewed-on: http://openocd.zylin.com/5655 Tested-by: jenkins Reviewed-by: Evgeniy Didin <didin@synopsys.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-05-14Make mem2array work with 64-bit addresses. (#475)Tim Newsome1-5/+6
Change-Id: I805389dc9934db5affe3c8059d9630acede956c1
2020-05-12cortex_m: make bit fields in cortex_m unsigned.iosabi2-31/+32
Expression like (0xffff << 16) evaluate to type int, which is not able to hold that value, producing a warning when compiling with -fsanitize=undefined. This patch makes most of the cortex_m constants unsigned using the BIT() macro or appending "ul" when possible to fix the undefined behavior warning. Signed-off-by: iosabi <iosabi@protonmail.com> Change-Id: I7af194305ef612d7a32e74eaf9f11dd85fa87f32 Reviewed-on: http://openocd.zylin.com/5583 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-05-09coding style: open function's brace at beginning of new lineAntonio Borneo2-21/+11
Issue identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types OPEN_BRACE -f {} \; Change-Id: I6d1356ed11e2699525f384efb7556bc2efdc299f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5628 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de>
2020-05-09coding style: wrap lines longer than 120 charsAntonio Borneo2-3/+13
The coding style is quite permissive allowing 120 chars per line, but abuses are still present. Fix them, wrapping the lines. Change-Id: I94d66b651d759a60ec35f7ba115c43933e70ed69 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5626 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-05-09coding style: let "else" follow the close braceAntonio Borneo1-2/+1
The statement "else" should not be on a new line when follows a close brace '}'. Fix it! Issue identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types ELSE_AFTER_BRACE -f {} \; Change-Id: I8af247ec3f75a69713d7cb1e73881254d16c189e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5623 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-05-09coding style: add missing space when split stringsAntonio Borneo3-9/+9
Long strings are split across few lines; usually split occurs at the white space between two words. Check that the space between the two words is still present. While there, adjust the amount of space between words. Issue identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types MISSING_SPACE -f {} \; Change-Id: I28b9a65564195ba967051add53d1c848c7b8fb30 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5620 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-05-09coding style: avoid unnecessary line continuationsAntonio Borneo4-19/+19
Line continuation, adding a backslash as last char of the line, is requested in multi-line macro definition, but is not necessary in the rest of C code. Remove it where present. Identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types LINE_CONTINUATIONS -f {} \; Change-Id: Id0c69e93456731717a7b290b16580e9f8ae741bc Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5619 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-05-09coding style: add parenthesis around the argument of sizeofAntonio Borneo7-20/+20
The script checkpatch available in new Linux kernel offers an experimental feature for automatically fix the code in place. While still experimental, the feature works quite well for simple fixes, like parenthesis. This patch has been created automatically with the script under review for inclusion in OpenOCD, using the command: find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types SIZEOF_PARENTHESIS --fix-inplace -f {} \; Change-Id: I8adb325bdb0e13211f8bae8b4770ec1979c176bf Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5618 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-05-09coding style: remove useless break after a goto or returnAntonio Borneo5-10/+0
In a switch/case statement, a break placed after a goto or return is never executed. The script checkpatch available in Linux kernel v5.1 issues a warning for such unused break statements. In the process of reviewing the new checkpatch for its inclusion in OpenOCD, let's get rid of these warnings. The script checkpatch is unable to fixup automatically this case. Thanks to having "break" command using a single code line, this patch has been generated using the script below: find src/ -type f -exec ./tools/scripts/checkpatch.pl -q \ --types UNNECESSARY_BREAK -f {} \; \ | sed -n '/^#/{s/^.*FILE: //;s/:$//;s/:/ /;p}' \ | awk 'function P() {print "sed -i '\''"b"'\'' "a}; { if ($1!=a) { if (a) {P()}; a=$1; b=$2"{d}"; } else { b=b";"$2"{d}" } }; END {P()}' Change-Id: I56ca098faa5fe8d1e3f712dc0a029a3f10559d99 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5617 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-05-08target/arc: introduce breakpoint functionalityEvgeniy Didin2-2/+162
With this patch we introduce set/unset breakpoints routines and add/remove bp handlers. Currently soft breakpoints are only supported. Changes since v1: * Change if-statement in arc_remove_breakpoint * Squash changes from http://openocd.zylin.com/#/c/5641/ in this commit to fix build. Change-Id: Ib10ccdb02fd1606e4f407f012b1bee106a8ffccd Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5641 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-05-08target/arc: introduce arc_read/write_instruction functionsEvgeniy Didin2-0/+79
This commit introduces helper instruction read/write functions for further bp functionality. Change-Id: I619fbe2870ef6365c29ed1618bb83b6f7eb84690 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5640 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
generated by cgit v1.1 at 2024-11-16 14:08:04 +0000