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2020-09-09Make a couple variables static.staticTim Newsome2-4/+2
2020-09-03Fix usage for our RISC-V commands. (#521)Tim Newsome2-24/+20
2020-09-03Check malloc/calloc return values. (#517)Tim Newsome4-9/+96
2020-09-01user4 0x23 should be MSB. (#519)Jiuyang Liu1-1/+7
2020-08-31Make checkpatch require Signed-off-by (#516)Tim Newsome2-3/+3
2020-08-24Add SPDX tags for RISC-V files. (#513)Tim Newsome12-0/+24
2020-08-24Update encoding.h from riscv-opcodes (#514)Tim Newsome5-256/+583
2020-08-24Update debug_defines.h from riscv-debug-spec (#515)Tim Newsome3-1700/+1783
2020-08-21Mostly whitespace changes. (#511)Tim Newsome4-35/+35
2020-08-18Update to version 1.0 of the vector spec. (#505)Tim Newsome1-1/+1
2020-08-18Create `riscv repeat_read` command (#510)Tim Newsome7-85/+180
2020-08-17Account for impebreak in size requirements for progbuf (#509)Samuel Obuch1-30/+26
2020-08-07Fix of DMI batch scans over 64-bits (#432)Jan Matyas4-27/+37
2020-07-17Further deprecate `-rtos riscv`. (#499)Tim Newsome1-0/+19
2020-07-07Triggers with type=0 aren't real. (#496)Tim Newsome1-1/+5
2020-07-02Merge pull request #494 from riscv/from_upstreamTim Newsome79-683/+8859
2020-07-01Warn if we are asked to read/write 0 bytes. (#492)Tim Newsome1-0/+10
2020-06-30Merge branch 'riscv' into from_upstreamTim Newsome2-6/+6
2020-06-25Don't halt the algorith-running hart because another is halted. (#490)Tim Newsome1-3/+1
2020-06-25Accept dmstatus.version==3 (0.14) (#489)Tim Newsome1-3/+5
2020-06-23Merge branch 'master' into from_upstreamTim Newsome79-683/+8859
2020-06-18Step/resume off manual hardware triggers (#486)Tim Newsome2-30/+119
2020-06-18target/armv7m_trace: Calculate prescaler for external capture devicesMarc Schink1-0/+16
2020-06-16riscv: Avoid shadowing read_csr/write_csr macros (#483)Khem Raj1-6/+6
2020-06-06coding style: fix multi-line dereferencingAntonio Borneo1-2/+2
2020-06-06target/cortex_a: fix memory leak of register cacheAntonio Borneo4-0/+25
2020-06-06target/mem_ap: fix two memory leaksAntonio Borneo1-0/+10
2020-06-06target/cortex-m: enable C_DEBUGEN during examineAntonio Borneo1-0/+13
2020-06-06arm_adi_v5: dap_ti_be_32_quirks_command minor simplificationTarek BOCHKATI1-18/+2
2020-06-06arm_adi_v5: enhance command error reportingTarek BOCHKATI1-17/+32
2020-05-26Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issu… (#479)Tommy Murphy1-3/+22
2020-05-24openocd: properly use jim data typesAntonio Borneo2-3/+4
2020-05-24stm8 target: make adapter speed settings workAke Rehnman1-11/+29
2020-05-24swim: fix adapter speed handlingAntonio Borneo1-1/+1
2020-05-24swim: abstract the transport in stm8 targetAntonio Borneo1-53/+16
2020-05-24arm_disassembler: fix typo 'ARM_UNKNOWN_INSTUCTION' to '.._INSTRUCTION'Tarek BOCHKATI2-2/+2
2020-05-19Fix semihosting for multicore targets (#478)Tim Newsome4-75/+131
2020-05-18Speed up SBA block reads roughly 2x. (#477)Tim Newsome1-3/+49
2020-05-14target/arc: fix build with clangAntonio Borneo1-1/+1
2020-05-14Make mem2array work with 64-bit addresses. (#475)Tim Newsome1-5/+6
2020-05-12cortex_m: make bit fields in cortex_m unsigned.iosabi2-31/+32
2020-05-09coding style: open function's brace at beginning of new lineAntonio Borneo2-21/+11
2020-05-09coding style: wrap lines longer than 120 charsAntonio Borneo2-3/+13
2020-05-09coding style: let "else" follow the close braceAntonio Borneo1-2/+1
2020-05-09coding style: add missing space when split stringsAntonio Borneo3-9/+9
2020-05-09coding style: avoid unnecessary line continuationsAntonio Borneo4-19/+19
2020-05-09coding style: add parenthesis around the argument of sizeofAntonio Borneo7-20/+20
2020-05-09coding style: remove useless break after a goto or returnAntonio Borneo5-10/+0
2020-05-08target/arc: introduce breakpoint functionalityEvgeniy Didin2-2/+162
2020-05-08target/arc: introduce arc_read/write_instruction functionsEvgeniy Didin2-0/+79
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