riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-07-16	target/riscv: single DMI accesses via batch	Evgeniy Naydanov	5	-272/+74
2024-07-10	target/riscv: write SB address using batch	Evgeniy Naydanov	1	-38/+37
2024-07-09	Merge pull request #1096 from en-sc/en-sc/run-batch-busy	Evgeniy Naydanov	1	-3/+7
2024-07-09	Merge pull request #1083 from en-sc/en-sc/deprecate-reset-timeout	Evgeniy Naydanov	4	-72/+41
2024-07-09	Merge pull request #1081 from en-sc/en-sc/sb_read_v1	Evgeniy Naydanov	1	-62/+32
2024-07-09	Merge pull request #1093 from en-sc/en-sc/v-ext-csrs	Evgeniy Naydanov	1	-0/+8
2024-07-04	target/riscv: deprecate `riscv set_reset_timeout_sec`	Evgeniy Naydanov	4	-72/+41
2024-07-04	Merge pull request #1082 from en-sc/en-sc/sbcs-read	Evgeniy Naydanov	1	-20/+8
2024-07-03	target/riscv: reset `dmi.busy` after batches	Evgeniy Naydanov	1	-3/+7
2024-07-03	target/riscv: vector CSRs are optional	Evgeniy Naydanov	1	-0/+8
2024-07-03	target/riscv: use batch interface in `read_memory_bus_v1()`	Evgeniy Naydanov	1	-62/+32
2024-07-03	Merge pull request #1087 from en-sc/en-sc/delay-types	Evgeniy Naydanov	3	-110/+167
2024-07-03	Merge pull request #1084 from en-sc/en-sc/ref-reg-files	Evgeniy Naydanov	17	-1486/+1678
2024-07-02	target/riscv: simplify `sbcs` read in `write_memory_bus_v1()`	Evgeniy Naydanov	1	-20/+8
2024-07-02	target/riscv: separate register cache stuff into files	Evgeniy Naydanov	17	-1486/+1678
2024-07-01	target/riscv: replace `info->*_delay` with `riscv_scan_delays`	Evgeniy Naydanov	3	-110/+167
2024-06-14	target/riscv: select DMI IR on batch access.	Evgeniy Naydanov	1	-0/+2
2024-06-10	Merge pull request #1073 from en-sc/en-sc/abs-reg-batch	Evgeniy Naydanov	3	-100/+308
2024-06-06	target/riscv: write registers using batch	Evgeniy Naydanov	3	-100/+308
2024-06-04	target/riscv: stop using register_get/set for 0.11 targets	Evgeniy Naydanov	2	-16/+102
2024-06-04	Revert "Initialize all registers in examine"	Evgeniy Naydanov	1	-2/+0
2024-06-04	Merge pull request #1056 from aap-sc/aap-sc/no_hit_bit_status	Anatoly Parshintsev	2	-15/+90
2024-05-31	riscv-013: Remove unused typedef slot_tremove-slot_t-from-riscv-013	Jan Matyas	1	-6/+0
2024-05-28	target/riscv: do not emit warnings when a non-existent CSR is hidden	Parshintsev Anatoly	1	-1/+1
2024-05-28	target/riscv: fix halt reason for targets that do not support hit bit on trig...	Parshintsev Anatoly	2	-15/+90
2024-05-28	Merge pull request #1033 from en-sc/en-sc/err-read-abs-arg	Evgeniy Naydanov	3	-80/+218
2024-05-23	target/riscv: read abstract args using batch	Evgeniy Naydanov	3	-80/+218
2024-05-18	Merge pull request #1061 from en-sc/en-sc/dm-reset	Evgeniy Naydanov	1	-41/+81
2024-05-17	Merge pull request #1029 from MrAlexei/add_decode_wp_rvc	Evgeniy Naydanov	1	-30/+467
2024-05-15	target/riscv: only `dmactive` can be written if `dmactive` is low	Evgeniy Naydanov	1	-41/+81
2024-05-02	Merge pull request #1028 from en-sc/en-sc/busy-reset-batch	Evgeniy Naydanov	5	-29/+45
2024-04-30	Add functions to decode RVC load and store instructions	Aleksey Lotosh	1	-30/+467
2024-04-27	Merge pull request #1031 from aap-sc/aap-sc/hart_status_info_fixup	Evgeniy Naydanov	1	-8/+31
2024-04-27	Merge pull request #1055 from aap-sc/aap-sc/bp_unitialized	Evgeniy Naydanov	1	-3/+7
2024-04-26	target/riscv: reset delays during batch scans	Evgeniy Naydanov	5	-29/+45
2024-04-26	Merge pull request #1025 from en-sc/en-sc/dump-field	Evgeniy Naydanov	5	-76/+49
2024-04-26	Merge pull request #1046 from en-sc/en-sc/reg-rv011-segfault-propper	Evgeniy Naydanov	1	-4/+4
2024-04-24	fix confusing status messages during resume	Parshintsev Anatoly	1	-8/+31
2024-04-24	target/riscv: use breakpoint_hw_set/watchpoint_set to properly initialize bp/...	Parshintsev Anatoly	1	-3/+7
2024-04-23	target/riscv/riscv-011: pc and dpc should be cached at the same location	Evgeniy Naydanov	1	-2/+2
2024-04-20	target/riscv/riscv-011.c: fix access to non-existent register	Evgeniy Naydanov	1	-4/+4
2024-04-19	target/riscv: decode DMI scans in batch access	Evgeniy Naydanov	5	-76/+49
2024-04-14	Merge pull request #1040 from rivos-eblot/dev/ebl/read_mem_dmibase	Evgeniy Naydanov	1	-1/+5
2024-04-14	Merge pull request #1023 from en-sc/en-sc/check-ac-busy	Evgeniy Naydanov	1	-80/+239
2024-04-11	target/riscv: check `abstractcs.busy`	Evgeniy Naydanov	1	-6/+73
2024-04-11	target/riscv: introduce `examine_dm()` function	Evgeniy Naydanov	1	-73/+131
2024-04-10	target/riscv: cache `abstractcs.busy` in `dm013_info_t`	Evgeniy Naydanov	1	-2/+36
2024-04-05	target/riscv: read registers are not valid on a running target	Evgeniy Naydanov	1	-1/+2
2024-04-04	target/riscv: Add missing DM base offset to read_memory_bus_v1()	Emmanuel Blot	1	-1/+5
2024-03-21	[NFC] target/riscv: refactor `init_registers()`	Evgeniy Naydanov	3	-379/+529