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riscv-tools/riscv-openocd.git
FE_402_fix
__archive__
add_macos_build
autoconf
bscan_optimization
bscan_tunnel
buf_sget
build32
busy
compliance_dev
debug-log-reg-failure
deinit
dmi_read
dmstatus_version
dsp5680_build
eclipse_memory_read
eclipse_multicore_fix
examine_command
examine_unavailable_harts
examine_unavailable_harts_backup
examine_unavailable_harts_rebase
examine_unavailable_harts_squash
fence_i_fix_for_release
fix-halt-reason-after-singlestep
fix_macbuild
gd32vf103
gdb_next_port
gitignore-build
global
halt_examine
haltreq
hypervisor_translate
jlink
log_output
macbuild
macro
manual_hwbp
master
mem64
mpsse_flush
multicore
new_bscan_approach
newprogram
nohartstatus
old_fixes_and_eclipse_memory_read
old_triggers
print_port
race
rbb_cleanup
regcache
regression_test_janmat_experim
release
remove-slot_t-from-riscv-013
reset_test
reverse-resume-order
riscv
riscv-batch-cleanup
riscv-compliance
riscv-compliance-dev
s2_increment
sba_tests
set_group
static
travis-nop
update_defines
us_xds110
vector2
winbuild
wip
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Author
Files
Lines
2018-02-06
Merge remote-tracking branch 'origin/riscv' into HEAD
Megan Wachs
1
-26
/
+33
2018-01-08
Propagate register read errors.
Tim Newsome
1
-6
/
+9
2017-12-27
Get rid of abort() calls.
Tim Newsome
1
-7
/
+8
2017-12-26
Remove unused code.
Tim Newsome
1
-2
/
+0
2017-12-26
Conform to OpenOCD style guide.
Tim Newsome
1
-1
/
+1
2017-12-19
WIP xml register for 0.11.
Tim Newsome
1
-1
/
+7
2017-12-19
`make all` debug tests now pass.
Tim Newsome
1
-0
/
+2
2017-10-27
Support 64-bit FPRs on RV32.
Tim Newsome
1
-0
/
+3
2017-10-25
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
Megan Wachs
1
-5
/
+5
2017-10-18
Pay attention to impebreak.
Tim Newsome
1
-0
/
+3
2017-10-16
Memtest{16,32} pass.
Tim Newsome
1
-5
/
+0
2017-10-12
WIP; doesn't work.
Tim Newsome
1
-4
/
+0
2017-09-26
Fix triggers for multi-gdb mode.
Tim Newsome
1
-1
/
+3
2017-09-19
Cleaning up single-hart reset.
Tim Newsome
1
-3
/
+0
2017-08-15
riscv: Add commands for setting timeouts
Megan Wachs
1
-0
/
+9
2017-08-15
riscv: Add commands for setting timeouts
Megan Wachs
1
-0
/
+9
2017-08-14
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
Megan Wachs
1
-0
/
+15
2017-07-12
Share trigger code between 0.11 and 0.13 code.
Tim Newsome
1
-0
/
+15
2017-07-12
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
Megan Wachs
1
-3
/
+6
2017-07-10
Disable debugger-set triggers on connect
Tim Newsome
1
-3
/
+6
2017-07-05
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
mwachs5
1
-1
/
+4
2017-06-28
riscv: Add skeleton of RISC-V v013 compliance
mwachs5
1
-0
/
+1
2017-06-21
Factor out checking if harts should be used
Palmer Dabbelt
1
-0
/
+3
2017-06-20
Set current_hartid from coreid
Palmer Dabbelt
1
-1
/
+1
2017-06-13
Fix the build.
Tim Newsome
1
-5
/
+6
2017-05-25
Invalidate the register cache on step, resume, reset
Palmer Dabbelt
1
-0
/
+3
2017-05-15
Build fixes
Palmer Dabbelt
1
-0
/
+3
2017-05-09
Allow all harts to be reset
Palmer Dabbelt
1
-0
/
+3
2017-04-26
Add 64-bit and multihart support
Palmer Dabbelt
1
-40
/
+181
2017-02-10
Attempt to discover XLEN with abstract reg reads
Tim Newsome
1
-0
/
+5
2017-02-05
Add missing header file.
Tim Newsome
1
-0
/
+62
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