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path: root/src/target/riscv/riscv.c
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2018-11-07Doxygen style, too. (#325)Tim Newsome1-1/+1
2018-11-05Conform to OpenOCD style. (#323)Tim Newsome1-1/+1
2018-11-05FIX(src/target/riscv/riscv.c): riscv_add_breakpoint: RVC: invalid 32bit trans...Pavel S. Smirnov1-10/+19
2018-10-30Old fixes from June (#311)Carsten Gosvig1-14/+23
2018-10-24Revert "Don't report exact watchpoint to gdb. (#300)" (#304)Tim Newsome1-5/+1
2018-10-18Fix segfault in riscv_deinit_target(). (#306)Tim Newsome1-6/+11
2018-09-06Don't report exact watchpoint to gdb. (#300)Tim Newsome1-1/+5
2018-08-31Merge remote-tracking branch 'origin/riscv' into sba_testssba_testsMegan Wachs1-0/+26
2018-08-29Fix typo.Tim Newsome1-1/+1
2018-08-29Merge branch 'riscv' into sba_testsTim Newsome1-142/+453
2018-08-29Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebaseMegan Wachs1-67/+269
2018-08-29Add command to expose custom registers (#293)Tim Newsome1-32/+118
2018-08-27Handle hardware watchpoints hit by RV32 loads and stores (#291)craigblackmore1-0/+84
2018-08-23Switch active rtos thread on any hart halt. (#290)Dmitry Ryzhov1-0/+1
2018-07-16Use work area instead of riscv-specific configTim Newsome1-35/+0
2018-06-12target/riscv: fix trailing spacesLiviu Ionescu1-10/+10
2018-06-12target/riscv: explain why `arm` commands are usedLiviu Ionescu1-0/+13
2018-06-12target/riscv: add semihosting supportLiviu Ionescu1-0/+53
2018-05-25Merge pull request #261 from riscv/trigger_enumv20180629Tim Newsome1-0/+11
2018-05-22Merge remote-tracking branch 'origin/trigger_enum' into riscv-complianceriscv-compliance-devMegan Wachs1-0/+11
2018-05-22Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs1-20/+14
2018-05-22Merge pull request #257 from riscv/commentTim Newsome1-0/+4
2018-05-22Delay trigger enumeration until it's required.Tim Newsome1-0/+11
2018-05-22Fix posible null deref in get_target_typeDan Robertson1-3/+10
2018-05-17Review feedback.Tim Newsome1-1/+1
2018-05-17Comment riscv_set_register, register_write_directTim Newsome1-0/+4
2018-05-14Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs1-1/+67
2018-05-08blank_check_memory prototype has changed.Tim Newsome1-17/+0
2018-05-07Don't error if hart select isn't implemented.Tim Newsome1-1/+1
2018-05-03counter*h registers only exist on RV32Tim Newsome1-0/+66
2018-04-30Merge branch 'riscv' into notice_resetTim Newsome1-18/+50
2018-04-18Merge remote-tracking branch 'origin/riscv' into HEADMegan Wachs1-5/+3
2018-04-18Enforce OpenOCD style guide. (#239)Tim Newsome1-5/+3
2018-04-17Merge remote-tracking branch 'origin/notice_reset' into riscv-complianceMegan Wachs1-38/+64
2018-04-16riscv-compliance: whitespace cleanupMegan Wachs1-14/+13
2018-04-13Fix issue with COMMAND_PARSE_NUMBERRyan Macdonald1-2/+3
2018-04-12Merge branch 'riscv' into riscv-complianceMegan Wachs1-29/+235
2018-04-11Added address alignment test, code fixups from reviewRyan Macdonald1-12/+16
2018-04-09Fix some build issuesRyan Macdonald1-3/+3
2018-04-09Change #ifdef SIM_ON to be a run-time argRyan Macdonald1-4/+9
2018-04-09Add #ifdef to only enable sbbusyerror test in simulation.Ryan Macdonald1-7/+7
2018-04-05Fixed build issuesRyan Macdonald1-4/+8
2018-04-05Checkpoint: finish debug of tests, working on hitting sbbusyerror caseRyan Macdonald1-5/+5
2018-04-04Initial commit of tests for SBA featureRyan Macdonald1-0/+28
2018-04-03Track misa per-hart even in -rtos modeTim Newsome1-14/+21
2018-04-02Add gdb_report_register_access_error commandTim Newsome1-1/+0
2018-03-30Merge pull request #230 from riscv/delegTim Newsome1-0/+8
2018-03-27Once more... Less sloppy this time.Tim Newsome1-1/+1
2018-03-27Don't rely on havereset when deasserting reset.Tim Newsome1-22/+0
2018-03-26Fix m*deleg logic.Tim Newsome1-2/+1
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