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path: root/src/target/riscv/riscv.c
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2020-09-01Prefix RISC-V globals with riscv_.globalTim Newsome1-34/+38
2020-09-01user4 0x23 should be MSB. (#519)Jiuyang Liu1-1/+7
2020-08-24Add SPDX tags for RISC-V files. (#513)Tim Newsome1-0/+2
2020-08-24Update encoding.h from riscv-opcodes (#514)Tim Newsome1-3/+3
2020-08-21Mostly whitespace changes. (#511)Tim Newsome1-11/+11
2020-08-18Create `riscv repeat_read` command (#510)Tim Newsome1-7/+53
2020-07-07Triggers with type=0 aren't real. (#496)Tim Newsome1-1/+5
2020-07-02Merge pull request #494 from riscv/from_upstreamTim Newsome1-59/+18
2020-07-01Warn if we are asked to read/write 0 bytes. (#492)Tim Newsome1-0/+10
2020-06-30Merge branch 'riscv' into from_upstreamTim Newsome1-3/+1
2020-06-25Don't halt the algorith-running hart because another is halted. (#490)Tim Newsome1-3/+1
2020-06-23Merge branch 'master' into from_upstreamTim Newsome1-59/+18
2020-06-18Step/resume off manual hardware triggers (#486)Tim Newsome1-30/+115
2020-05-26Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issu… (#479)Tommy Murphy1-3/+22
2020-05-19Fix semihosting for multicore targets (#478)Tim Newsome1-39/+85
2020-05-09coding style: open function's brace at beginning of new lineAntonio Borneo1-19/+9
2020-05-09coding style: add missing space when split stringsAntonio Borneo1-6/+6
2020-05-06Don't cache PC, but do cache DPC. (#473)Tim Newsome1-3/+4
2020-05-06Add awareness of halt group cause. (#472)Tim Newsome1-0/+1
2020-04-21Cache accesses through riscv_[sg]et_register. (#467)Tim Newsome1-15/+71
2020-04-13Don't propagate failure to read satp in riscv_mmu() (#466)Tim Newsome1-3/+4
2020-04-10Expose FPRs as single and double for F and D. (#465)Tim Newsome1-1/+17
2020-03-27Document default values for some config options. (#461)Tim Newsome1-3/+4
2020-03-26Deal with vlenb being unreadable. (#458)Tim Newsome1-1/+1
2020-03-10semihosting: reorganize semihosting commandsTarek BOCHKATI1-37/+2
2020-03-07helper/binarybuffer: fix clang static analyzer warningsTomas Vanek1-4/+4
2020-03-05Fix address translation when high bits are set. (#453)Tim Newsome1-6/+21
2020-02-20Give control over dcsr.ebreak[msu] bits. (#451)Tim Newsome1-0/+57
2020-02-14Add support for vector register access (#448)Tim Newsome1-26/+235
2020-01-06Upcast mask value to work with 64-bit physical (#436)Tim Newsome1-3/+7
2019-12-31Fix bugs. Do not touch SATP if there is no MMU. (#435)Hsiangkai1-3/+5
2019-12-10riscv: translate virtual address to physical address. (#425)Hsiangkai1-0/+222
2019-12-04Remove unused data structure. (#431)Tim Newsome1-5/+1
2019-11-22Fix memory access on some targets. (#428)Tim Newsome1-1/+9
2019-11-12BSCAN batch fix (#422)Greg Savin1-0/+40
2019-11-04Add support for 64-bit memory reads/writes (#419)Tim Newsome1-3/+4
2019-10-23pmpcfg[13] only exist on RV32. (#416)Tim Newsome1-0/+2
2019-09-27Merge branch 'master' into from_upstreamTim Newsome1-20/+23
2019-09-09Fix flashing HiFive Unleashed (#402)Tim Newsome1-10/+30
2019-08-26Use only one hart to run algorithm. (#396)Tim Newsome1-5/+18
2019-07-18Access memory through the scope of current privilege level (#386)Nils Wistoff1-0/+21
2019-07-15Make resume order configurable. (#388)Tim Newsome1-7/+58
2019-07-09Redo fespi flash algorithm (#384)Tim Newsome1-0/+64
2019-07-08RV32E support (#387)Tim Newsome1-12/+30
2019-06-19Improve block read and checksum speed (#381)Tim Newsome1-8/+93
2019-06-10Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)Paul George1-64/+117
2019-05-14helper/command: change prototype of command_print/command_print_samelineAntonio Borneo1-2/+2
2019-05-09Simultaneous halt (#372)Tim Newsome1-118/+148
2019-04-23Support for driving RISC-V DM via Arty's own JTAG chain using BSCAN tunnel (#...Greg Savin1-0/+159
2019-04-10target/riscv: Free registers to avoid memory leakMarc Schink1-14/+17
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