riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-06-20	Don't immediately segfault with -rtos on v0.11.	Tim Newsome	1	-0/+3
2017-06-15	Fix indentation to match OpenOCD style.	Tim Newsome	1	-38/+38
2017-06-15	Jump to the RTOS hartid after halting	Palmer Dabbelt	1	-0/+7
2017-06-13	Fix the build.	Tim Newsome	1	-19/+20
2017-05-25	Invalidate the register cache when rtos_hartid==-1	Palmer Dabbelt	1	-1/+4
2017-05-25	Invalidate the register cache on step, resume, reset	Palmer Dabbelt	1	-0/+11
2017-05-11	Shim back in some old interfaces for now	Palmer Dabbelt	1	-16/+72
2017-05-09	Allow all harts to be reset	Palmer Dabbelt	1	-37/+85
2017-05-05	Avoid accessing null target->reg_cache	Megan Wachs	1	-0/+6
2017-05-01	Correct previous hart caching logic	Palmer Dabbelt	1	-1/+2
2017-04-26	Keep calling the old poll on v0.11 targets	Palmer Dabbelt	1	-2/+11
2017-04-26	riscv: Fix some blocking compile warnings	Megan Wachs	1	-2/+2
2017-04-26	Add 64-bit and multihart support	Palmer Dabbelt	1	-8/+497
2017-04-10	riscv: Implement the assert/deassert reset functions for v13	Megan Wachs	1	-0/+3
2017-02-10	Attempt to discover XLEN with abstract reg reads	Tim Newsome	1	-27/+0
2017-02-05	Use the csrNNN name instead of "mstatus".	Tim Newsome	1	-2/+6
2017-02-05	Most gdbserver tests pass now.	Tim Newsome	1	-2296/+89
2017-01-25	riscv: disable interrupts for all priviledge levels	Megan Wachs	1	-3/+2
2017-01-25	riscv: Use proper UINT packing and unpacking routines for disabling interrupt...	Megan Wachs	1	-5/+12
2017-01-25	riscv: Globally disable interrupts when running algorithms.	Megan Wachs	1	-0/+12
2016-12-07	riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you just...	Megan Wachs	1	-0/+30
2016-12-01	Fix issue #6: build failure on gcc 6	Tim Newsome	1	-1/+1
2016-11-25	Cope better if the target unexpectedly resets.	Tim Newsome	1	-4/+11
2016-11-18	Flash at 8KB/s, using 10,000 byte working area.	Tim Newsome	1	-0/+2
2016-11-16	Use algorithm to speed up fespi flash programming.	Tim Newsome	1	-1/+109
2016-11-01	Make fpu regs work even if mstatus.fs is 0.	Tim Newsome	1	-7/+87
2016-10-27	Fix bug with slow targets.	Tim Newsome	1	-11/+14
2016-10-24	Add some comments.	Tim Newsome	1	-0/+44
2016-10-20	Make CLI step and resume work.	Tim Newsome	1	-24/+26
2016-10-20	Use reg_cache structure, to make reg command work.	Tim Newsome	1	-64/+78
2016-10-14	Print when we're ready for gdb to connect.	Tim Newsome	1	-0/+6
2016-10-13	Be quiet when the target is just running normally.	Tim Newsome	1	-1/+0
2016-10-11	Use an easily changed constant for timeout.	Tim Newsome	1	-3/+4
2016-10-10	Display pc to the user in 'monitor reset init'.	Tim Newsome	1	-2/+13
2016-10-03	Change invalid access from error to user message.	Tim Newsome	1	-2/+2
2016-09-29	Fix off-by-one error in assert.	Tim Newsome	1	-9/+9
2016-09-29	Clear dmode triggers when we first halt the target	Tim Newsome	1	-19/+42
2016-09-29	Deal with dbus being busy in all cases.	Tim Newsome	1	-17/+43
2016-09-27	Read idle, and test all debug RAM.	Tim Newsome	1	-17/+73
2016-09-27	Only write to existing dram. Clear dbus error.	Tim Newsome	1	-45/+55
2016-09-23	Improve low-level logging.	Tim Newsome	1	-40/+79
2016-09-23	Make more code use the scans "class".	Tim Newsome	1	-178/+152
2016-09-23	Implement hardware triggers that match spec.	Tim Newsome	1	-157/+428
2016-09-23	Optimize read a bit.	Tim Newsome	1	-31/+39
2016-09-23	Properly mark the cache as clean after its written	Tim Newsome	1	-3/+3
2016-09-23	Convert some more code for 64-bit.	Tim Newsome	1	-16/+17
2016-09-23	Properly write 64-bit PCs.	Tim Newsome	1	-2/+2
2016-09-23	WIP for 64-bit support.	Tim Newsome	1	-158/+345
2016-09-23	Stop using conditional writes.	Tim Newsome	1	-16/+18
2016-09-23	Check for business in block reads.	Tim Newsome	1	-2/+11