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path: root/src/target/riscv/riscv-013.c
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2020-09-01Prefix RISC-V globals with riscv_.globalTim Newsome1-6/+6
2020-08-24Add SPDX tags for RISC-V files. (#513)Tim Newsome1-0/+2
2020-08-24Update encoding.h from riscv-opcodes (#514)Tim Newsome1-8/+8
2020-08-24Update debug_defines.h from riscv-debug-spec (#515)Tim Newsome1-458/+458
2020-08-21Mostly whitespace changes. (#511)Tim Newsome1-22/+22
2020-08-18Update to version 1.0 of the vector spec. (#505)Tim Newsome1-1/+1
2020-08-18Create `riscv repeat_read` command (#510)Tim Newsome1-52/+91
2020-08-17Account for impebreak in size requirements for progbuf (#509)Samuel Obuch1-30/+26
2020-08-07Fix of DMI batch scans over 64-bits (#432)Jan Matyas1-6/+6
2020-06-30Merge branch 'riscv' into from_upstreamTim Newsome1-3/+5
2020-06-25Accept dmstatus.version==3 (0.14) (#489)Tim Newsome1-3/+5
2020-06-23Merge branch 'master' into from_upstreamTim Newsome1-12/+5
2020-05-19Fix semihosting for multicore targets (#478)Tim Newsome1-2/+1
2020-05-18Speed up SBA block reads roughly 2x. (#477)Tim Newsome1-3/+49
2020-05-09coding style: avoid unnecessary line continuationsAntonio Borneo1-2/+2
2020-05-09coding style: remove useless break after a goto or returnAntonio Borneo1-2/+0
2020-05-06Add awareness of halt group cause. (#472)Tim Newsome1-0/+3
2020-04-21Remove BUILD_TARGET64Florian Fainelli1-6/+0
2020-03-27Fix some clang static checker complaints. (#464)Tim Newsome1-1/+5
2020-03-26Deal with vlenb being unreadable. (#458)Tim Newsome1-2/+6
2020-03-07helper/binarybuffer: fix clang static analyzer warningsTomas Vanek1-1/+2
2020-02-24coding style: fix space around pointer's asteriskAntonio Borneo1-1/+1
2020-02-20Give control over dcsr.ebreak[msu] bits. (#451)Tim Newsome1-3/+3
2020-02-14Add support for vector register access (#448)Tim Newsome1-21/+251
2020-01-27Complain about debug version before authentication. (#441)Tim Newsome1-3/+7
2020-01-13Handle DMI busy in sba write. (#437)Tim Newsome1-49/+49
2020-01-10Don't issue extra FENCE+FENCE.i for the current hart. (#439)Jan Matyas1-0/+4
2019-11-27Fixed write_memory_progbuf() on RV64. (#426)Jan Matyas1-1/+1
2019-11-22Fix memory access on some targets. (#428)Tim Newsome1-0/+24
2019-11-20Fix: Take into account progbuf writability. (#424)Jan Matyas1-2/+6
2019-11-12BSCAN batch fix (#422)Greg Savin1-44/+2
2019-11-04Add support for 64-bit memory reads/writes (#419)Tim Newsome1-48/+98
2019-10-03The compliance test is poorly supported.Tim Newsome1-1/+5
2019-09-24Perform SBA writes with batch transactions for improved performance. (#405)darius-bluespec1-18/+52
2019-09-09Fix flashing HiFive Unleashed (#402)Tim Newsome1-6/+7
2019-08-26Use only one hart to run algorithm. (#396)Tim Newsome1-6/+1
2019-08-19Adds support for RISCV Access Memory Abstract Commands (#394)dave-estes-syzexion1-6/+192
2019-07-26Properly detect errors in SBA reads. (#392)Tim Newsome1-19/+26
2019-07-18Access memory through the scope of current privilege level (#386)Nils Wistoff1-0/+88
2019-07-15Optimize reading a single byte/short/word. (#390)Tim Newsome1-4/+61
2019-07-15Write all ones to clear cmderr. (#389)Tim Newsome1-1/+1
2019-06-21Reduce abstract command execution by one scan. (#383)Tim Newsome1-37/+40
2019-06-19Improve block read and checksum speed (#381)Tim Newsome1-1/+20
2019-06-14Set mstatus.FS to access FPU CSRs. (#380)Tim Newsome1-3/+12
2019-06-10Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)Paul George1-18/+31
2019-05-21Don't write sbcs while sbbusy is set. (#375)Tim Newsome1-9/+24
2019-05-20RISC-V: Make compliance tests more verbose (#366)Philipp Wagner1-2/+10
2019-05-20RISC-V compliance test: target must be examined (#367)Philipp Wagner1-0/+6
2019-05-09Simultaneous halt (#372)Tim Newsome1-44/+68
2019-04-23Support for driving RISC-V DM via Arty's own JTAG chain using BSCAN tunnel (#...Greg Savin1-2/+52
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