aboutsummaryrefslogtreecommitdiff
path: root/src/target/cortex_a.c
AgeCommit message (Collapse)AuthorFilesLines
2024-05-11cortex_a: drop cortex_a_dap_write_memap_register_u32()Antonio Borneo1-52/+39
Historically, the function cortex_a_dap_write_memap_register_u32() was used to discriminate the register write in APB-AP CPU debug against the complex memory access in AHB-AP memory bus. It has no sense to keep the function and its comment. Plus, by forcing atomic write it impacts the debug performance. Drop it! A further rework to enqueue sequence of atomic writes is needed. Change-Id: I2f5e9015f0e27fa5a6d8337a1ae25e753e2e1d26 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8231 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins
2024-05-11cortex_a: drop the command 'cache auto'Antonio Borneo1-6/+2
The command 'cache auto' was introduced with commit cd440bd32a12 ("add armv7a_cache handlers") in 2015 to allow disabling the cache handling done automatically by OpenOCD. This was probably a way to test the cache handling when there were still the two independent accesses for APB-AP CPU debug and for AHB-AP memory bus. The handling of cache for cortex_a is robust and there is no more reason to disable it. The command 'cache auto' is not used in any upstream script. On target aarch64 this command has never been introduced as the cache is always handled automatically by OpenOCD. Drop the command 'cache auto' and add it in the deprecated list. Drop the flag 'auto_cache_enabled' by considering it as true. Rename the function 'armv7a_cache_auto_flush_all_data()' as 'armv7a_cache_flush_all_data()' and, while there, fix the error propagation in SMP case. Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8230 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2024-05-11cortex_a: drop useless cache invalidate on mem writeAntonio Borneo1-3/+0
The initial OpenOCD code for Cortex-A (ARMv7a) [1] was merged in 2009 but, due to lack of public documentation for ARMv7a, it was almost a simple copy/paste from the existing code for Cortex-M (ARMv7m). On Cortex-M the same AP provides access to both CPU debug and CPU memory. This feature is not present on ARMv7a. To still keep some communality with ARMv7m code, the change [2] splits the CPU debug access from the CPU memory access by using two independent AP; this is copied from the system architecture of TI OMAP3530 which provides to DAP a direct AHB-AP memory bus on AP#0, separated from AP#1 for the APB-AP CPU debug. But the direct memory access through the system bus breaks the coherency between memory and CPU caches, so change [3] added some cache invalidation to avoid issues. The code to allow ARMv7a CPU to really read/write in CPU memory was added by change [4] in 2011. Such still not optimized implementation was very slow, so it did not replace the access through the system bus. A selection through DAP's 'apsel" command was used to select between the two modes. Only in 2015, with change [5], the speed of CPU read/write was improved using the DCC_FAST_MODE. But the direct access to the memory through the system bus remained. Finally, with change [6] in 2018 the system bus access was dropped for good, as the new virtual target "mem_ap" could implement such access in a more clean way. Only memory access through CPU remained for ARMv7a. Nevertheless, a useless cache invalidation remained in the code, decreasing the speed of the write access. Drop the useless cache invalidate on CPU memory write and the associated comment, not anymore valid. Drop the now unused function armv7a_cache_auto_flush_on_write(). This provides a speedup of between 4 and 8, depending on adapter and JTAG/SWD speed. Link: [1] 7a93100c2dfe ("Add minimalist Cortex A8 file") Link: [2] 1d0b276c9f75 ("The rest of the Cortex-A8 support from Magnus: ...") Link: [3] d4e4d65d284f ("Cache invalidation when writing to memory") Link: [4] 05ab8bdb813a ("cortex_a9: implement read/write memory through APB-AP") Link: [5] 0228f8e8274d ("Cortex A: fix extra memory read and non-word sizes") Link: [6] fac9be64d944 ("target/cortex_a: remove buggy memory AP accesses") Change-Id: Ifa3c7ddf2698b2c87037fb48f783844034a7140e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8229 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2024-05-04target: cortex_a: fix regs invalidation when -defer-examineAntonio Borneo1-1/+1
The code for cortex_a allocates the register cache during the very first examine of the target. To prevent a segmentation fault in assert_reset(), the call to register_cache_invalidate() is guarded by target_was_examined(). But for targets with -defer-examine, the target is set as not examined in handle_target_reset() just before entering in assert_reset(). This causes registers to not be invalidated while reset a target examined but with -defer-examine. Change the condition and invalidate the register cache if it has been already allocated. Change-Id: I81ae782ddce07431d5f2c1bea3e2f19dfcd6d1ce Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8215 Tested-by: jenkins
2023-12-01target: clarify usage of `coreid`Evgeniy Naydanov1-11/+8
By definition in `target/target.h`, `coreid` is not a unique identifier of a target -- it can be the same for targets on different TAPs. Change-Id: Ifce78da55fffe28dd8b6b06ecae7d8c4e305c0a2 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7997 Tested-by: jenkins Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-14arm_opcode: Add support for ARM MCRR/MRRCFlorian Fainelli1-0/+47
Add support for the ARM MCRR/MRRC instructions which require the use of two registers to transfer a 64-bit co-processor registers. We are going to use this in a subsequent patch in order to properly dump 64-bit page table descriptors that exist on ARMv7A with VMSA extensions. We make use of r0 and r1 to transfer 64-bit quantities to/from DCC. Change-Id: Ic4975026c1ae4f2853795575ac7701d541248736 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Michael Chalfant <michael.chalfant@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5228 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-29target: fix messages and return values of failed op because not haltedTomas Vanek1-5/+5
Lot of messages was logged as LOG_WARNING, but the operation failed immediately. Sometimes no error message was logged at all. Add missing messages, change warnings to errors. Sometimes ERROR_TARGET_INVALID was returned. Some command handlers returned ERROR_OK! Always return ERROR_TARGET_NOT_HALTED. While on it use LOG_TARGET_ERROR() whenever possible. Prefix command_print() message with 'Error:' to get closer to LOG_TARGET_ERROR() variant. Error message was not added to get() and set() methods of struct xxx_reg_type - the return value is properly checked and a message is logged by the caller in case of ERROR_TARGET_NOT_HALTED. Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: I2fe4187c6025f0038956ab387edbf3f461c69398 Reviewed-on: https://review.openocd.org/c/openocd/+/7819 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-13openocd: trivial replace of jim-nvp with new nvpAntonio Borneo1-8/+9
For some trivial case only, replace calls to jim-nvp with calls to the new OpenOCD nvp. Change-Id: Ifd9aff32b67748af8ab808e6a6b6e64f5271b888 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7553 Tested-by: jenkins
2022-12-17target: cortex_a: fix clang error core.CallAndMessageAntonio Borneo1-10/+8
Clang complains about the variable 'orig_dfsr' that can be used uninitialized both in cortex_a_read_cpu_memory() and in cortex_a_write_cpu_memory(). The issue is caused by an incorrect error path that used to jump through 'goto out'. The code after the label 'out' is specific to handle the case of an error during memory R/W; it is incorrect to jump there to handle an error during the initialization that precedes the memory R/W. Replace the 'goto out' with 'return retval'. Remove the label 'out' that is now unused. Change-Id: Ib4b140221d1c1b63419de109579bde8b63fc2e8c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7393 Tested-by: jenkins
2022-12-17arm_adi_v5: fix SIGSEGV due to failing re-examineAntonio Borneo1-17/+14
Commit 35a503b08d14 ("arm_adi_v5: add ap refcount and add get/put around ap use") modifies the examine functions of mem_ap, cortex_m, cortex_a and aarch64 by calling dap_put_ap() and then looking again for the mem-ap and calling dap_get_ap(). This causes an issue if the system is irresponsive and the examine fails and left the AP pointer to NULL. If the system was already examined the NULL pointer will cause a SIGSEGV. Commit b6dad912b85d ("target/cortex_m: prevent segmentation fault in cortex_m_poll()") proposes a fix for one specific case and only on cortex_m. Modify all the examine functions by skipping look-up for the AP if it was already set in a previous examine; the target's AP is not supposed to change during runtime. Remove the partial fix for cortex_m as it is not needed anymore. Change-Id: I806ec3b1b02fcc76e141c8dd3a65044febbf0a8c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: 35a503b08d14 ("arm_adi_v5: add ap refcount and add get/put around ap use") Reviewed-on: https://review.openocd.org/c/openocd/+/7392 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-18openocd: fix SPDX tag format for files .cAntonio Borneo1-1/+1
With the old checkpatch we cannot use the correct format for the SPDX tags in the file .c, in fact the C99 comments are not allowed and we had to use the block comment. With the new checkpatch, let's switch to the correct SPDX format. Change created automatically through the command: sed -i \ 's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \ $(find src/ contrib/ -name \*.c) Change-Id: I6da16506baa7af718947562505dd49606d124171 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7153 Tested-by: jenkins
2022-09-13openocd: remove CamelCase symbols *xPSR*Antonio Borneo1-4/+4
We have left the camelcase symbols *xPSR* for some time, to avoid any conflict with possibly pending patches in gerrit. With the approaching v0.12.0-rc1, it's time to revisit it. The patches in gerrit that conflict with this rename are all not merge-able due to conflicts or due to negative review. Drop these CamelCase symbols. Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7155 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-07-23openocd: src/target: replace the GPL-2.0-or-later license tagAntonio Borneo1-13/+2
Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7071 Tested-by: jenkins
2022-06-24arm_adi_v5: add ap refcount and add get/put around ap useAntonio Borneo1-2/+14
While an ADIv5 DAP can only have 256 AP, ADIv6 can provide till 2**40 (1,099,511,627,776) AP per DAP. The actual trivial code implementation for ADIv5 (that uses an array of 256 ap in the struct adiv5_dap) cannot be extended as-is to handle ADIv6. The simple array of 256 AP can be reused as a dynamic storage for ADIv6 ap: - the ADIv5 AP number is replaced by the ADIv6 base address; - the index of the array (equal to ADIv5 AP number) has no link to any ADIv6 property; - the ADIv6 base_address has to be searched in the array of AP. The 256 elements in the AP array should be enough for any device available today. In future it can be easily increased, if needed. To efficiently use the 256 elements in the AP array, the code should associate one element of the array to an ADIv6 AP (through the AP base address), then cancel the association when the AP is not anymore needed. This is important to avoid saturating the AP array while exploring the device through 'dap apreg' commands. Add a reference counter in the struct adiv5_ap to track how many times the struct has been associated with the same base address. Introduce the function dap_get_ap() to associate and return the struct, and dap_put_ap() to release the struct. For the moment the code covers ADIv5 only, so the association is through the index. Use the two functions above and dap_find_get_ap() throughout the code. Check the return value of dap_get_ap(). It is always not NULL in the current ADIv5-only implementation, but can be NULL for ADIv6 when there are no more available AP in the array. Instrument dap_queue_ap_read() and dap_queue_ap_write() to log an error message if the AP has reference counter zero, meaning that the AP has not been 'get' yet. This helps identifying AP used without get/put, e.g. code missed by this patch, or merged later. Instrument dap_cleanup_all() to log an error message if an AP has reference counter not zero at openocd exit, meaning that the AP has not been 'put' yet. Change-Id: I98316eb42b9f3d9c9bbbb6c73b1091b53f629092 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6455 Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Tested-by: jenkins
2022-05-14arm_adi_v5: let dap_lookup_cs_component() to get AP dbgbaseAntonio Borneo1-9/+2
Simplify the code in cortex_a and aarch64 by moving the call to dap_get_debugbase() inside dap_lookup_cs_component(). This has the further effects: - dap_get_debugbase() is not referenced outside arm_adi_v5.c and becomes static; - dap_lookup_cs_component() looses one parameter; - the coreid parameter 'idx' is passed as value; - the caller in aarch64 don't have and don't print the irrelevant value of AP register APID; - fixes the debug message in the caller in aarch64 to print the coreid value instead of always zero. Change-Id: Ic7f0f643fdf067c059c8f2455a02ff18a3fed054 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6823 Tested-by: jenkins
2022-03-19target: Rework 'set' variable of break-/watchpointsMarc Schink1-24/+24
The 'set' variable name suggests a boolean data type which determines whether a breakpoint (or watchpoint) is active. However, it is also used to store the number of the breakpoint. This encoding leads to inconsistent value assignments: boolean and integer values are mixed. Also, associated hardware comparator numbers, which are usually numbered from 0, cannot be used directly. An additional offset is required to store the comparator numbers. In order to make the code more readable and the value assignment more consistent, change the variable name to 'is_set', its data type to 'bool' and introduce a dedicated variable for the break-/watchpoint number. In order to make the review easier, the data types of various related variables (e.g. number of breakpoints) are not changed. While at it, fix a few coding style issues. Change-Id: I2193f5639247cce6b80580d4c1c6afee916aeb82 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/6319 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-14target/smp: use a struct list_head to hold the smp targetsAntonio Borneo1-17/+9
Instead of reinventing a simply linked list, reuse the list helper for the list of targets in a smp cluster. Using the existing helper, that implements a double linked list, makes trivial going through the list in reverse order. Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6783 Tested-by: jenkins
2021-09-25arm_coresight: add include file and use itAntonio Borneo1-2/+3
Several magic numbers related to ARM CoreSight specification IHI0029E are spread around OpenOCD code. Define through macros the ARM CoreSight magic numbers and collect them in a single include file. Use the new macros wherever possible. Change-Id: I9b0c1c651ce4ffbaf08d31791ef16e95983ee4cb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6446 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2021-09-18openocd: remove last NULL comparisonsAntonio Borneo1-3/+3
The NULL pointers preceded by cast where not detected by the scripting tools looking for NULL pointer comparison. Remove them and, while there, further simplify the code and apply the other coding style rules. Change-Id: Ia7406122e07ef56ef311579ab0ee7ddb22c8e4b5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6539 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-08-22cortex_a: use the ap number specified at target createAntonio Borneo1-5/+10
Current implementation ignores the flag '-ap-num' provided to command 'target create' and searches for the first AP of APB type. If specified, use the ap number. Change-Id: If1ac12345220d14a4a60515efe46dc2a2eac079a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6413 Tested-by: jenkins
2021-07-24openocd: remove NULL comparisons with checkpatch [1/2]Antonio Borneo1-2/+2
Patch generated automatically through the new checkpatch with flags "--types COMPARISON_TO_NULL --fix-inplace". This only fixes the comparisons if (symbol == NULL) if (symbol != NULL) The case of NULL on the left side of the comparison is not tested. Some automatic fix is incorrect and has been massaged by hands: - if (*psig == NULL) + if (*!psig) changed as + if (!*psig) Change-Id: If4a1e2b4e547e223532e8e3d9da89bf9cb382ce6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6351 Tested-by: jenkins
2021-07-24openocd: fix simple cases of NULL comparisonAntonio Borneo1-5/+5
There are more than 1000 NULL comparisons to be aligned to the coding style. For recurrent NULL comparison it's preferable using trivial scripts in order to minimize the review effort. Patch generated automatically with the command: sed -i PATTERN $(find src/ -type f) where PATTERN is in the list: 's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g' Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6350 Tested-by: jenkins
2021-07-20openocd: fix simple cases of Yoda conditionAntonio Borneo1-3/+3
There are ~900 Yoda conditions to be aligned to the coding style. For recurrent Yoda conditions it's preferable using a trivial script in order to minimize the review effort. E.g. comparison of uppercase macro/enum with lowercase variable: - ...(ERROR_OK == retval)... + ...(retval == ERROR_OK)... Patch generated automatically with the command: sed -i \ 's/(\([A-Z][A-Z0-9_]*\) \([=!]=\) \([a-z][a-z0-9_]*\))/(\3 \2 \1)/g' \ $(find src/ -type f) While there, remove the braces {} around a single statement block to prevent warning from checkpatch. Change-Id: If585b0a4b4578879c87b2dd74d9e0025e275ec6b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6354 Tested-by: jenkins Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20target/arm: rename CamelCase symbolsAntonio Borneo1-31/+31
No major cross dependencies, mostly changes internal to each file/function. Change-Id: I3f0879f0f33c6badc36a0dc60229323978a7e280 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6338 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-02target/cortex_a: Replace printf() with LOG_DEBUG()Marc Schink1-2/+2
Change-Id: I38fa8e21959b398033741cbd779b632d572c7ce4 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6336 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-02target/adiv5: Large Physical Address ExtensionKevin Burke1-2/+2
Provides ARM LPAE support to allow 64-bit TAR setting on MEM AP accesses. Tested on a 4-core ARM ARES Processor system using an AXI Access Port. Change-Id: I88f7a0a57a6abb58665032929194a41dd8729f6b Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com> Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Reviewed-on: http://openocd.zylin.com/5576 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-18target: Rename 'linked_BRP' to 'linked_brp'Marc Schink1-3/+3
Change-Id: I9dd67ac3e8cd5dd9cdeffce56020b387a8f298fa Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6316 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-13target/cortex_a: Use bool data typeMarc Schink1-11/+11
Change-Id: Ieea3dc05809263aa0eba5125d52fef3fe77e9c5a Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6289 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-04helper/jim-nvp: comply with coding style [2/2]Antonio Borneo1-8/+8
With the API fixed to comply with OpenOCD coding style, fix all the references in the code. Patch generated automatically with the script below. The list is in reverse order to replace a common prefix after the replacement of the symbols with the same prefix. %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- (cat << EOF Jim_SetResult_NvpUnknown jim_set_result_nvp_unknown Jim_Nvp_value2name_simple jim_nvp_value2name_simple Jim_Nvp_value2name_obj jim_nvp_value2name_obj Jim_Nvp_value2name jim_nvp_value2name Jim_Nvp_name2value_simple jim_nvp_name2value_simple Jim_Nvp_name2value_obj_nocase jim_nvp_name2value_obj_nocase Jim_Nvp_name2value_obj jim_nvp_name2value_obj Jim_Nvp_name2value_nocase_simple jim_nvp_name2value_nocase_simple Jim_Nvp_name2value_nocase jim_nvp_name2value_nocase Jim_Nvp_name2value jim_nvp_name2value Jim_Nvp struct jim_nvp Jim_GetOpt_Wide jim_getopt_wide Jim_GetOpt_String jim_getopt_string Jim_GetOpt_Setup jim_getopt_setup Jim_GetOpt_Obj jim_getopt_obj Jim_GetOpt_NvpUnknown jim_getopt_nvp_unknown Jim_GetOpt_Nvp jim_getopt_nvp Jim_GetOpt_Enum jim_getopt_enum Jim_GetOpt_Double jim_getopt_double Jim_GetOpt_Debug jim_getopt_debug Jim_GetOptInfo struct jim_getopt_info Jim_GetNvp jim_get_nvp Jim_Debug_ArgvString jim_debug_argv_string EOF ) | while read a b; do sed -i "s/$a/$b/g" $(find src -type f ! -name jim-nvp.\? ) done %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I10a12bd64bb8b17575fd9150482c989c92b298a2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6184 Reviewed-by: Marc Schink <dev@zapb.de> Tested-by: jenkins
2021-06-03target/cortex_a: fix memory leak on watchpointsAntonio Borneo1-0/+1
The memory allocated to hold the watchpoints is not freed at OpenOCD exit. Free the watchpoint memory at OpenOCD exit. Change-Id: I518c9ce0dc901cde2913d752e3154734f878b854 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6210 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-06-03target/cortex_a: add support for watchpoint length of 1, 2 and 4 bytesAntonio Borneo1-5/+41
Use byte address select for 1 and 2 bytes length. Use normal mode for 4 bytes length. Change-Id: I28d182f25145d0635de64d0361d456f1ad96640e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6197 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-06-03target/cortex_a: fix number of watchpointsAntonio Borneo1-2/+6
Decrement the available watchpoints only when succeed setting it. Initialize the available watchpoint with the correct value. Change-Id: I0f93b347300b8ebedbcd9e718d4ba32b26cf6846 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6196 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-06-03target/cortex_a: add support for watchpointsChengyu Zheng1-4/+186
The current implementation of OpenOCD does not support watchpoints for cortex_a architecture. So, I replaced the add_watchpoint and remove_watchpoint with the specific implementation for the cortex a and using the breakpoint implementation and the arm documentation [1] as reference. In particular, I have made the following changes: * added the following functions - cortex_a_add_watchpoint This wrapper function check whether there are any watchpoint available on the target device by calling cortex_a_set_watchpoint. - cortex_a_set_watchpoint This function is responsible for settings the watchpoint register pair. In particular, it sets the WVR and the WCR registers with the cortex_a_dap command. - cortex_a_remove_watchpoint This wrapper function the selected watchpoint on the target device by calling cortex_a_unset_watchpoint. - cortex_a_unset_watchpoint This function sets both the WVR and the WCR registers to zero, thus unsetting the watchpoint. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BCGDHIEJ.html Change-Id: I86611dab474cb84836662af572b17636dc68e282 Signed-off-by: Chengyu Zheng <chengyu.zheng@polimi.it> Reviewed-on: http://openocd.zylin.com/3913 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Marc Schink <dev@zapb.de> Tested-by: jenkins
2021-03-19target: remove target names already deprecated in v0.8.0Antonio Borneo1-1/+0
Some target name were marked as deprecated in release v0.7.0 and v0.8.0, almost 7 years ago, and replaced with more 'actual' names. We can reasonably expect that in these 7 years any user of OpenOCD has already migrated to v0.8.0 or to some newer release, thus has already updated any local/personal script to get rid of the deprecated message. Drop the target names already deprecated in v0.8.0. Change-Id: I7c7491496db1b302b4eb1e9fc6090b58d4acf05a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6086 Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-12-26cortex-a: fix reset on dapdirect transportsAntonio Borneo1-2/+2
The target code for assert reset on cortex_a has been patched on commit b0698501b0e7 ("cortex_a: fix cortex_a_assert_reset() if srst_gates_jtag") then in cdba6ba0ad63 ("cortex_a: fix reset for SWD transport") to workaround the mismatch between jtag and swd implementations. See discussion for the second patch at http://openocd.zylin.com/3641/ While all of these mismatches should hopefully be cleaned by the reset framework rework, an extension of the workaround of the second patch is required for dapdirect transports, either dapdirect_swd and dapdirect_jtag. Extend the existing workaround to all non-jtag transports. Change-Id: Ia6a9d43bab524cbb3de4c37ce24c45f25187353d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5979 Tested-by: jenkins
2020-11-04target: declare local symbols as staticAntonio Borneo1-1/+2
Functions and variables that are not used outside the file should be declared as static. Change-Id: I9f97571a528f0cb3c3c26f873577ab16fdec3cdc Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5895 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-09-05target: use proper format with uint32_tAntonio Borneo1-4/+4
Modify the format strings to properly handle uint32_t data types. While there, fix prototype mismatch between header and C file of the function armv7a_l1_d_cache_inval_virt(). Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5818 Tested-by: jenkins
2020-07-26target: fix minor typos and duplicated wordsAntonio Borneo1-1/+1
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5766 Tested-by: jenkins
2020-06-06target/cortex_a: fix memory leak of register cacheAntonio Borneo1-0/+1
There is no method to free the register cache, allocated in armv4_5, so we get a memory leak. Issue identified by valgrind. Implement the method arm_free_reg_cache() and call it in cortex_a deinit and to exit for error during arm_dpm_setup(). Tested on dual cortex-A stm32mp15x. This change is inspired from similar fix in commit b01b5fe13a67 ("armv7m: Fix memory leak in register caching."). The same allocation is also used by target types "arm7tdmi", "arm9tdmi", "arm11" and "xscale" but they all lack the deinit method and I do not have relevant HW to test the fix. For such reasons they are not addressed in this patch. Change-Id: I4da1e1f12e36ec245d1f3b11a4eafcbd9a1d2e25 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5693 Tested-by: jenkins
2020-04-12cortex_a: don't wait for target halted in deassert_reset()Antonio Borneo1-1/+3
The tcl script src/target/startup.tcl has already the proper centralized support to wait for all targets to halt after the command "reset halt". The extra wait in cortex_a_deassert_reset() is not required. This extra wait is also an issue for multi-core support, because waiting for one core to halt can delay the halt request to the other cores. Replace the indirect call to cortex_a_halt(), that embeds the wait for halt, with a low-level halt sequence. The on-going work on the reset framework is compatible with this change; in fact it keeps in startup.tcl the wait for targets to halt, even if current code proposal for cortex_a simply removes the function cortex_a_deassert_reset(). Change-Id: Ic661c3791a29ba7d520e31f85a61f939a646feb5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5472 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-03-12target/cortex_a: add hypervisor modeAntonio Borneo1-0/+9
Hypervisor mode is present only if the optional virtualization extensions are available. Moreover, virtualization extensions require that also security extensions are implemented. Add the required infrastructure for the shadowed registers in hypervisor mode. Make monitor shadowed registers visible in hypervisor mode too. Make hypervisor shadowed registers visible in hypervisor mode only. Check during cortex_a examine if virtualization extensions are present and then conditionally enable the visibility of both hypervisor and monitor modes shadowed registers. Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5261 Tested-by: jenkins
2020-03-12armv7a: access monitor registers only with security extensionsAntonio Borneo1-2/+11
Accordingly to ARM DDI 0406C at B1.5, the security extensions for armv7a are optional extensions and can be detected by reading ID_PFR1. The monitor mode is part of the security extensions and the shadow registers "sp_mon", "lr_mon" and "spsr_mon" are only present with the security extensions. Read the register ID_PFR1 during cortex_a examine, determine if security extension is present and then conditionally enable the visibility of the monitor mode shadow registers. Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5259 Tested-by: jenkins
2020-03-12arm: Use different enum for core_type and core_modeAntonio Borneo1-1/+1
The fields core_type and core_mode use the same enum arm_mode but encode different information, making the code less immediate to read. Use a different enum arm_core_type for the field core_type. The code behavior is not changed. Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5258 Tested-by: jenkins
2020-03-12cortex_a: warn on broken debug_base settingMatthias Welwarsky1-0/+4
A common problem with target configurations appears to be broken debug base address configuration. ARM DDI0406C.d specifies in App. D, 1.4.1, that bit 31 of the debug base address serves as identification of an external debugger, as opposed to an internal access to memory mapped debug registers by the CPU. External accesses are treated as privileged and require no debug authentification via the lock access register. Sometimes the base address of a debug component is wrong even in the targets' ROM table. In this case, the correct base address must be specified using the -dbgbase argument when creating the target. This patch adds a warning when bit 31 of the debug base address is not set, as a hint to the user. Change-Id: I9c41d85a138123c657ef655e3436a2aa39249dcc Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/5105 Tested-by: jenkins Reviewed-by: Tommy Vestermark <tov@vestermark.dk> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-10-18target/cortex_a: Extract code to read/write from/to register to/from DCCFlorian Fainelli1-13/+38
In preparation for supporting the ARM MCRR and MRRC commands which will require using two 32-bit registers to read/write a 64-bit internal register, extract the common logic to read/write from/to a register to/from DCC and make that parameterized such that we can do this through not just r0. Change-Id: Iadb73f5cde8cf5961b5a18ddd198bf39d791e610 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-on: http://openocd.zylin.com/5227 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-10-18target/cortex_a: use aligned accesses for read/write cpu memory slowAntonio Borneo1-4/+37
Armv7a is able to read and write memory at un-aligned address, but only when bit SCTLR.A (Alignment check enable) is zero and the address belongs to a memory space with attribute "Normal" (see [1] chapter A3.2.1 "Unaligned data access"). In all the other cases the memory access will trigger an alignment fault data abort exception. Memory attributes are explained in [1] chapter A3.5 "Memory types and attributes and the memory order model". Disabling the MMU cause a change in memory attribute, as explained in [1] chapter B3.2 "The effects of disabling MMUs on VMSA behavior". This can cause several issues. e.g. a SW breakpoint on un-aligned 4-byte Thumb instruction, set when MMU is on, can be impossible to remove when MMU turns off. While is possible to check all the possible conditions before an un-aligned memory access, it's clearly more maintainable to skip such complexity and only perform aligned accesses. Check the alignment and eventually modify the data size before calling the functions cortex_a_{read,write}_cpu_memory_slow(). Change the comment in the two functions above to comply with the new behaviour. [1] ARM DDI 0406C.d - "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition" Change-Id: I57b4c11e7fa7e78aaaaee4406a5734b48db740ae Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5138 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-14target/cortex_a: remove dependency from jtag queueAntonio Borneo1-2/+3
Replace jtag specific API jtag_add_reset() with transport independent API adapter_{de}assert_reset(). Change-Id: I1b917a4c1205115c4e0315373d81a9305e931258 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4944 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-12armv7a_mmu: Do not restrict virtual addresses to uint32_tFlorian Fainelli1-1/+1
In preparation for adding super section decoding, do not restrict armv7a_mmu_translate_va_pa() to 32-bit virtual addresses since ARMv7-A processors with VMSA extensions (including LPAE) can issue wider physical addresses. Update casting to uint32_t where necessary. Change-Id: Id1c3d0d5ac324cbdc334259d9ea75fe4981671a1 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-on: http://openocd.zylin.com/5211 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-05-14helper/command: change prototype of command_print/command_print_samelineAntonio Borneo1-2/+2
To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-14target/armv7a: change prototype of armv7a_handle_cache_info_command()Paul Fertser1-1/+1
To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should be ready to switch to CMD as first parameter. Change prototype of armv7a_handle_cache_info_command() to pass CMD instead of CMD_CTX. This change was part of http://openocd.zylin.com/1815 from Paul Fertser and has been extracted and rebased to simplify the review. Change-Id: I27f507869cb41c74722a759e69dfd45658fcd4be Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5069 Tested-by: jenkins
generated by cgit v1.1 at 2024-08-16 04:29:30 +0000