index
:
riscv-tools/riscv-openocd.git
FE_402_fix
__archive__
add_macos_build
autoconf
bscan_optimization
bscan_tunnel
buf_sget
build32
busy
compliance_dev
debug-log-reg-failure
deinit
dmi_read
dmstatus_version
dsp5680_build
eclipse_memory_read
eclipse_multicore_fix
examine_command
examine_unavailable_harts
examine_unavailable_harts_backup
examine_unavailable_harts_rebase
examine_unavailable_harts_squash
fence_i_fix_for_release
fix-halt-reason-after-singlestep
fix_macbuild
gd32vf103
gdb_next_port
gitignore-build
global
halt_examine
haltreq
hypervisor_translate
jlink
log_output
macbuild
macro
manual_hwbp
master
mem64
mpsse_flush
multicore
new_bscan_approach
newprogram
nohartstatus
old_fixes_and_eclipse_memory_read
old_triggers
print_port
race
rbb_cleanup
regcache
regression_test_janmat_experim
release
remove-slot_t-from-riscv-013
reset_test
reverse-resume-order
riscv
riscv-batch-cleanup
riscv-compliance
riscv-compliance-dev
s2_increment
sba_tests
set_group
static
travis-nop
update_defines
us_xds110
vector2
winbuild
wip
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arc.h
Age
Commit message (
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Author
Files
Lines
2023-02-03
target: arc: rewrite command 'arc add-reg' as COMMAND_HANDLER
Antonio Borneo
1
-10
/
+0
2022-08-14
target: consolidate existing target/algo common_magic
Tomas Vanek
1
-2
/
+2
2022-07-23
openocd: src: fix incorrect SPDX tags
Antonio Borneo
1
-2
/
+2
2021-05-22
target: fix some minor typo
Antonio Borneo
1
-1
/
+1
2021-03-19
target/arc: refactor ARC register numbers defines
Evgeniy Didin
1
-3
/
+46
2020-09-05
target: use proper format with uint32_t
Antonio Borneo
1
-1
/
+1
2020-07-26
target/arc: Introduce Actionpoints support
Evgeniy Didin
1
-2
/
+32
2020-06-27
target/arc: Introduce L1I,L1D,L2 caches support
Evgeniy Didin
1
-0
/
+37
2020-05-08
target/arc: introduce breakpoint functionality
Evgeniy Didin
1
-0
/
+6
2020-05-08
target/arc: introduce arc_read/write_instruction functions
Evgeniy Didin
1
-0
/
+23
2020-05-08
target/arc: Add initial stepping functions
Evgeniy Didin
1
-1
/
+6
2020-02-29
target/arc: fix clang static analyzer warnings
Evgeniy Didin
1
-0
/
+4
2020-02-27
Introduce ARCv2 architecture related code
Evgeniy Didin
1
-0
/
+212