| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2021-03-19 | target/arc: refactor ARC register numbers defines | Evgeniy Didin | 1 | -3/+46 |
| 2020-09-05 | target: use proper format with uint32_t | Antonio Borneo | 1 | -1/+1 |
| 2020-07-26 | target/arc: Introduce Actionpoints support | Evgeniy Didin | 1 | -2/+32 |
| 2020-06-27 | target/arc: Introduce L1I,L1D,L2 caches support | Evgeniy Didin | 1 | -0/+37 |
| 2020-05-08 | target/arc: introduce breakpoint functionality | Evgeniy Didin | 1 | -0/+6 |
| 2020-05-08 | target/arc: introduce arc_read/write_instruction functions | Evgeniy Didin | 1 | -0/+23 |
| 2020-05-08 | target/arc: Add initial stepping functions | Evgeniy Didin | 1 | -1/+6 |
| 2020-02-29 | target/arc: fix clang static analyzer warnings | Evgeniy Didin | 1 | -0/+4 |
| 2020-02-27 | Introduce ARCv2 architecture related code | Evgeniy Didin | 1 | -0/+212 |
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index : riscv-tools/riscv-openocd.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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