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2023-03-28Merge fd2b4e36e591cd165dfdbf121ca9e68f04f644c9 into a01bd76e5c10eba8bc3481eb7...openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461Tim Newsome1-3/+17
2023-03-28Preserve artifact of Linux build, too.Tim Newsome1-3/+17
2023-03-22Merge pull request #818 from riscv/windows_buildopenocd64-d486b21Tim Newsome1-0/+6
2023-03-21Upload Windows binary as artifact.Tim Newsome1-0/+6
2023-03-20Merge pull request #815 from riscv/s_aiaTim Newsome5-96/+250
2023-03-16Merge pull request #800 from en-sc/en-sc/try-all-trigs-in-maybe-add-trigTim Newsome1-185/+245
2023-03-16Expose S?aia CSRs if they're on the target.Tim Newsome4-3/+88
2023-03-16Update encoding.h.Tim Newsome1-93/+162
2023-03-15Merge pull request #812 from XuHangHub/riscvTim Newsome1-5/+5
2023-03-15Try all triggers in maybe_add_trigger_t2 and _t6Evgeniy Naydanov1-185/+245
2023-03-13Merge pull request #811 from riscv/address_inTim Newsome1-2/+1
2023-03-12target/riscv: fix the bug of using S2 register in read_memory_progbufHang Xu1-5/+5
2023-03-10target/riscv: Remove unused address_in variable.Tim Newsome1-2/+1
2023-03-08Calculate the FreeRTOS type sizes and offsets more adaptively. (#806)Chao Du2-6/+55
2023-03-07Merge pull request #807 from riscv/from_upstreamTim Newsome65-440/+7139
2023-03-06Merge branch 'riscv' into from_upstreamTim Newsome1-1/+1
2023-03-06Merge pull request #810 from riscv/snapshotTim Newsome1-1/+1
2023-03-06workflow: Use ubuntu-20.04 to build snapshotTim Newsome1-1/+1
2023-03-06helper: Add missing entry to jep106.inc.Tim Newsome1-0/+1
2023-03-06flash: Remove duplicate entry for micron mt25qu01.Tim Newsome1-1/+0
2023-03-01Don't check the HACKING file.Tim Newsome1-0/+1
2023-02-28Merge commit 'd1b882f2c014258be5397067e45848fa5465b78b' into from_upstreamTim Newsome62-439/+7137
2023-02-28Merge pull request #802 from riscv/regression_testTim Newsome1-0/+76
2023-02-20Merge pull request #801 from Du-Chao/freertosTim Newsome1-0/+1
2023-02-17Smoke test OpenOCD against spike.Tim Newsome1-0/+76
2023-02-17Set the current_thread when no FreeRTOS task was created.Chao Du1-0/+1
2023-02-16Merge pull request #799 from riscv/icountTim Newsome2-17/+146
2023-02-15target/riscv: hide_csrs configuration option (#787)Anatoly Parshintsev3-0/+65
2023-02-15Add command "exec_progbuf" (#795)Jan Matyas4-9/+98
2023-02-15Merge pull request #796 from Du-Chao/freertos_logTim Newsome1-1/+1
2023-02-15Clarify that RISC-V triggers are optional.Tim Newsome1-2/+3
2023-02-15Add `riscv icount` command.Tim Newsome2-15/+143
2023-02-14Merge pull request #794 from riscv/fix-fence-instructionTim Newsome4-7/+8
2023-02-10Merge pull request #797 from riscv/Zve32Tim Newsome3-39/+65
2023-02-10Don't reuse a single riscv_program.Tim Newsome1-5/+7
2023-02-10If XLEN=64 and vsew=64 fails, fall back to vsew=32.Tim Newsome3-27/+51
2023-02-10Merge pull request #798 from aap-sc/aap-sc/mcounteren_fixupTim Newsome1-0/+3
2023-02-10CSR_MCOUNTEREN should not exist if U-mode is not supportedParshintsev Anatoly1-0/+3
2023-02-08Print out debug value after the assignment is made.Tim Newsome1-1/+1
2023-02-08Move yes_no_maybe_t into riscv.h.Tim Newsome2-6/+6
2023-02-08Improve a debug log in freertos_update_threads()duchao1-1/+1
2023-02-01Fix opcode for the "fence" instructionJan Matyas4-7/+8
2023-01-18Merge pull request #786 from aap-sc/aap-sc/vcsr_supportTim Newsome3-0/+3
2023-01-10target/riscv: added support for missing VCSR registerParshintsev Anatoly3-0/+3
2023-01-04Merge pull request #777 from riscv/itriggerTim Newsome3-22/+326
2023-01-03target/riscv: Remove `riscv test_sba_config_reg` command. (#780)Tim Newsome3-404/+0
2023-01-03target/riscv: Use unsigned int for trigger indexes.Tim Newsome1-7/+12
2023-01-03target/riscv: Read back tdata2 in set_trigger()Tim Newsome1-4/+14
2023-01-02target/riscv: Add `riscv etrigger` command.Tim Newsome3-0/+133
2023-01-02target/riscv: Add `riscv itrigger` command.Tim Newsome3-7/+163
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