riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-04-14	Remove the hart_state variablenohartstatus	Palmer Dabbelt	4	-88/+47
2017-04-14	Replace the 0.13-specific "program_t" with a generic one	Palmer Dabbelt	10	-566/+1254
2017-04-10	Remove Off By 1 FIXME because HW is fixed	mwachs5	1	-3/+1
2017-04-07	Implement the "vCont" GDB packet	Palmer Dabbelt	7	-13/+74
2017-04-07	typo in comment	Megan Wachs	1	-1/+1
2017-04-07	Determine the trigger count dynamically	Palmer Dabbelt	3	-9/+39
2017-04-07	Determine the hart count dynamically	Palmer Dabbelt	4	-1/+24
2017-04-06	Call riscv_xlen() to support 32-bit FESPI targets	Palmer Dabbelt	1	-4/+6
2017-04-06	Add a RISC-V RTOS, which natievly supports multiple harts	Palmer Dabbelt	11	-948/+1396
2017-04-04	Merge pull request #28 from sifive/readmem_autoexec	Megan Wachs	1	-11/+27
2017-04-04	riscv: move value read to after autoexec is cleared.	Megan Wachs	1	-8/+15
2017-04-04	riscv: Correct the autoexec in read_mem	Megan Wachs	1	-4/+13
2017-03-30	Merge pull request #23 from sifive/w1-to-clear-cmderr	Palmer Dabbelt	1	-9/+5
2017-03-30	riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.	Megan Wachs	1	-9/+5
2017-03-23	Revert "(WIP) Force algorithms to 64 bit"	Palmer Dabbelt	1	-2/+2
2017-03-23	(WIP) Force algorithms to 64 bit	Palmer Dabbelt	1	-2/+2
2017-03-23	some device	Palmer Dabbelt	1	-0/+1
2017-03-23	Don't set abstractauto at the start	Palmer Dabbelt	1	-1/+2
2017-03-22	Merge pull request #21 from sifive/read_memory_retry	Palmer Dabbelt	1	-66/+75
2017-03-22	Merge remote-tracking branch 'origin/riscv' into read_memory_retry	Megan Wachs	0	-0/+0
2017-03-22	riscv: Retry failed memory reads	Megan Wachs	1	-65/+75
2017-03-22	Turn off autoexec after read_memory()	Palmer Dabbelt	1	-0/+1
2017-03-21	riscv: add missing variable declaration.	Megan Wachs	1	-0/+1
2017-03-21	Clear autoexec correctly	Palmer Dabbelt	1	-1/+1
2017-03-21	Wrong autoexec	Palmer Dabbelt	1	-2/+2
2017-03-21	Builds	Palmer Dabbelt	2	-425/+533
2017-03-21	Merge pull request #20 from sifive/delay_after_autoexec	Megan Wachs	1	-3/+10
2017-03-15	riscv-v13: wait for idle in read_memory	Megan Wachs	1	-3/+10
2017-02-27	Remove more cruft.	Tim Newsome	1	-35/+1
2017-02-27	Merge pull request #18 from sifive/halt_correctly	Tim Newsome	1	-2/+4
2017-02-27	riscv: Ensure that hart is halted before attempting to examine it.	Megan Wachs	1	-2/+4
2017-02-25	Remove cruft.	Tim Newsome	1	-47/+11
2017-02-25	Use DCSR constants from the debug spec.	Tim Newsome	1	-170/+21
2017-02-25	Update bits to latest spec.	Tim Newsome	2	-587/+591
2017-02-22	Speed things up by ignoring return values.	Tim Newsome	1	-13/+45
2017-02-21	Optimize memory write code, used in download.	Tim Newsome	1	-92/+216
2017-02-20	Better error checking in memory access.	Tim Newsome	1	-4/+8
2017-02-20	Properly restore s0 and s1 on resume.	Tim Newsome	1	-8/+8
2017-02-17	Fix access FPU registers again.	Tim Newsome	1	-46/+80
2017-02-17	Fix use of REG vs CSR constants.	Tim Newsome	1	-26/+30
2017-02-17	Bunch of register access refactoring.	Tim Newsome	2	-546/+161
2017-02-16	Check busy before triggering another command.	Tim Newsome	1	-46/+50
2017-02-15	Check for errors after read/write.	Tim Newsome	1	-4/+12
2017-02-15	Fix double read, which might have side effects.	Tim Newsome	1	-4/+6
2017-02-15	Make MemTest32 pass.	Tim Newsome	1	-2/+2
2017-02-15	Some memory access works.	Tim Newsome	2	-351/+161
2017-02-14	Merge pull request #15 from sifive/get_set_reg_error	Tim Newsome	2	-9/+45
2017-02-14	Make general CSR reads work.	Tim Newsome	1	-36/+22
2017-02-14	Make it all the way through examine().	Tim Newsome	1	-220/+85
2017-02-14	More dbus->dmi.	Tim Newsome	1	-21/+65