riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-06-18	Fix whitespace.manual_hwbp	Tim Newsome	1	-4/+2
2020-06-17	Also disable/reenable triggers around single step.	Tim Newsome	1	-77/+105
2020-06-17	Enumerate triggers when resuming from a trigger	Tim Newsome	1	-0/+3
2020-06-16	Accommodate users setting custom triggers.	Tim Newsome	2	-21/+81
2020-06-16	riscv: Avoid shadowing read_csr/write_csr macros (#483)	Khem Raj	1	-6/+6
2020-06-09	Add RISC-V to README. (#482)	Tim Newsome	1	-1/+1
2020-05-26	Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issu… (#479)	Tommy Murphy	1	-3/+22
2020-05-19	Fix semihosting for multicore targets (#478)	Tim Newsome	5	-76/+132
2020-05-18	Speed up SBA block reads roughly 2x. (#477)	Tim Newsome	1	-3/+49
2020-05-15	Improvements for the HiFive1 revB (#476)	Alistair Francis	3	-1/+3
2020-05-14	Make mem2array work with 64-bit addresses. (#475)	Tim Newsome	1	-5/+6
2020-05-06	Don't cache PC, but do cache DPC. (#473)	Tim Newsome	1	-3/+4
2020-05-06	Add awareness of halt group cause. (#472)	Tim Newsome	3	-0/+5
2020-04-21	Cache accesses through riscv_[sg]et_register. (#467)	Tim Newsome	2	-17/+75
2020-04-13	Don't propagate failure to read satp in riscv_mmu() (#466)	Tim Newsome	1	-3/+4
2020-04-10	Expose FPRs as single and double for F and D. (#465)	Tim Newsome	1	-1/+17
2020-03-27	Document default values for some config options. (#461)	Tim Newsome	2	-9/+10
2020-03-27	Fix some clang static checker complaints. (#464)	Tim Newsome	2	-17/+21
2020-03-26	Use the correct thread for memory accesses. (#459)	Tim Newsome	5	-5/+82
2020-03-26	Deal with vlenb being unreadable. (#458)	Tim Newsome	3	-3/+8
2020-03-19	Add support for HiFive1 RevB board (#456)	Jonathan Tinkham	5	-2/+30
2020-03-18	Update to 1.11 privileged spec. (#455)	Tim Newsome	1	-261/+347
2020-03-05	helper: skip including sys/sysctl.h on Linux (#450)	Tim Newsome	1	-0/+3
2020-03-05	Fix address translation when high bits are set. (#453)	Tim Newsome	2	-6/+23
2020-02-20	Give control over dcsr.ebreak[msu] bits. (#451)	Tim Newsome	5	-6/+87
2020-02-14	Add support for vector register access (#448)	Tim Newsome	7	-51/+1776
2020-01-31	Update the current thread when gdb requests a step. (#444)	Tim Newsome	1	-4/+5
2020-01-27	Complain about debug version before authentication. (#441)	Tim Newsome	1	-3/+7
2020-01-13	Handle DMI busy in sba write. (#437)	Tim Newsome	2	-55/+54
2020-01-10	Don't issue extra FENCE+FENCE.i for the current hart. (#439)	Jan Matyas	1	-0/+4
2020-01-06	Upcast mask value to work with 64-bit physical (#436)	Tim Newsome	1	-3/+7
2019-12-31	Fix bugs. Do not touch SATP if there is no MMU. (#435)	Hsiangkai	1	-3/+5
2019-12-10	riscv: translate virtual address to physical address. (#425)	Hsiangkai	4	-1/+246
2019-12-05	Increase maximum number of harts (#429)	bluew	1	-1/+1
2019-12-04	Remove unused data structure. (#431)	Tim Newsome	2	-10/+1
2019-12-04	Warn about using `-rtos riscv`. (#430)	Tim Newsome	1	-0/+7
2019-11-27	Fixed write_memory_progbuf() on RV64. (#426)	Jan Matyas	1	-1/+1
2019-11-22	Fix memory access on some targets. (#428)	Tim Newsome	4	-4/+37
2019-11-20	Fix: Take into account progbuf writability. (#424)	Jan Matyas	1	-2/+6
2019-11-15	fespi: Properly support large flash devices (#421)	Tim Newsome	5	-92/+126
2019-11-12	BSCAN batch fix (#422)	Greg Savin	5	-45/+73
2019-11-04	Add support for 64-bit memory reads/writes (#419)	Tim Newsome	8	-56/+142
2019-10-23	pmpcfg[13] only exist on RV32. (#416)	Tim Newsome	1	-0/+2
2019-10-14	Merge pull request #417 from riscv/heterogeneous	Tim Newsome	1	-2/+74
2019-10-11	Combine SMP group registers into one list for gdb	Tim Newsome	1	-2/+74
2019-10-09	Merge pull request #413 from riscv/compliance	Tim Newsome	1	-1/+5
2019-10-03	The compliance test is poorly supported.	Tim Newsome	1	-1/+5
2019-09-30	Merge pull request #411 from riscv/from_upstream	Tim Newsome	198	-4575/+3531
2019-09-30	Fix filterdiff line.	Tim Newsome	1	-1/+1
2019-09-27	Fix the build.	Tim Newsome	2	-18/+5