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2023-04-28target/riscv: Support VS-stage and G-stage address translation.hypervisor_translateTim Newsome1-5/+212
These are used in hypervisor mode. Change-Id: I5f773816f73c83b4ae57727fbc3b36b65b6185eb Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-25target/riscv: Refactor to create riscv_effective_privilege_mode()Tim Newsome1-7/+34
Change-Id: I65bba63a7bde746b0069133f8a42529d1d857d3e Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-25target/riscv: Move some code from riscv_address_translate() to riscv_virt2phys()Tim Newsome1-53/+55
Also minor code cleanups, and better debug messages. Change-Id: Iffc9951c8b38da2e3516926108b93db91883680e Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-25Comment pte_shiftTim Newsome1-0/+1
Change-Id: I48ad7637ff37898ca2df0f48501cf2c72fa1e722
2023-04-25target/riscv: Add constants for vsatp, hgatpTim Newsome2-0/+5
Change-Id: I130a8f7a7abc294bbdf60e7e0ce0bccb72bf920a Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-13workflow: Run checkpatch against diff with riscv (#822)Tim Newsome1-3/+7
* workflow: Run checkpatch against pull request only Instead of arbitrarily picking 20 changes. Change-Id: I5ec488aa4faa0b06056aa91d0432cda1674967b7 Signed-off-by: Tim Newsome <tim@sifive.com> * Display FETCH_HEAD in the log Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> --------- Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2023-04-12Preserve artifact of Linux build, too. (#828)Tim Newsome1-6/+24
* Preserve artifact of Linux build, too. That can be handy to e-mail to people who don't have a build setup. Change-Id: I7b7e2d6f0033edf71f53211168f74b80ada64b97 Signed-off-by: Tim Newsome <tim@sifive.com> * workflow: Run Linux build on Ubuntu 20.04, which is LTS. This makes the binaries more useful. Change-Id: I0cf6df68f03c4161222baa222c466fe0004ea769 Signed-off-by: Tim Newsome <tim@sifive.com> * Use checkoutv3 Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> --------- Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2023-04-11Merge pull request #835 from en-sc/en-sc/fix-err-resumeTim Newsome1-2/+2
target/riscv: Handle error code in resume_prep
2023-04-11Merge pull request #833 from zqb-all/read_log128Tim Newsome1-31/+40
target/riscv: support log memory access128 for read
2023-04-10target/riscv: Handle error code in resume_prepEvgeniy Naydanov1-2/+2
If hart can't change pc (e.g. it is running), resume command should fail. Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Change-Id: I14627366d574d806ea16262b7d305d8161f8bcc2
2023-04-10target/riscv: support log memory access128 for readMark Zhuang1-31/+40
Change-Id: I9235150fa00c03a1d75d0b44a7500758daa56e2b Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-04-07Merge pull request #823 from panciyan/riscvTim Newsome1-1/+1
target/riscv: leaf PTE check PTE_W missing
2023-04-06Merge pull request #821 from en-sc/en-sc/fix-reset-mhartsTim Newsome1-91/+62
target/riscv: simplify reset for rtos harts
2023-04-06Merge pull request #830 from zqb-all/csr_32bitTim Newsome1-2/+12
target/riscv: set some csr size to 32
2023-04-05Merge pull request #825 from riscv/hypervisorTim Newsome2-3/+9
target/riscv: Set hypervisor bits.
2023-04-05Merge branch 'riscv' into hypervisorTim Newsome1588-13975/+27065
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-05target/riscv: simplify resetEvgeniy Naydanov1-91/+62
Since the deletion of `-rtos hwthread`, there is no need to treat harts with `-rtos` specified differently on reset. Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Change-Id: I88a9129936b5172bb7479dfa1255e29ff460c054
2023-04-05Merge pull request #816 from riscv/from_upstreamTim Newsome1588-13878/+26962
Merge up to commit '1293ddd65713d6551775b67169387622ada477c1' from upstream
2023-04-04Merge pull request #819 from zqb-all/fix_size_assertTim Newsome3-90/+96
target/riscv: support log memory access128
2023-04-04flash/nor/spi: Move mt25ql02 to match upstream.Tim Newsome1-1/+1
Change-Id: I7537c122d581ec1848a1e7902874506e0bbb6e31 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-03target/riscv: set some csr size to 32Mark Zhuang1-2/+12
Change-Id: I4703b7b8ad492b14dc8d188ebb8f645c568fd515 Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-30Merge pull request #829 from XuHangHub/riscvTim Newsome1-3/+3
doc/openocd.texi: fix expose_csrs example
2023-03-29Merge pull request #824 from riscv/aiaTim Newsome1-3/+3
target/riscv: AIA regs, check for H not V
2023-03-29target/riscv: Set hypervisor bits.Tim Newsome2-3/+9
No other attempt is made at doing anything hypervisor-specific. Are other things necessary? Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-29doc/openocd.texi: fix expose_csrs exampleHang Xu1-3/+3
The first part of the command should be only "riscv expose_csrs", the $_TARGETNAME value is not necessarily "riscv", in fact it is generally riscv.cpux. Signed-off-by: Hang Xu <xuhang@eswincomputing.com>
2023-03-28Merge pull request #826 from riscv/icount_maskmaxTim Newsome1-1/+1
target/riscv: Don't ignore maskmax for icount.
2023-03-25target/riscv: [NFC] rename variables named read/writeMark Zhuang3-74/+54
read/write is system function Change-Id: I75db4dd5a1c60e9cff8a58a863a887beffc37cab Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25target/riscv: support log memory access128Mark Zhuang1-18/+44
Change-Id: I6b22c97f81fac26703b66d3dbd8b6d41aaea4875 Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-24target/riscv: Don't ignore maskmax for icount.Tim Newsome1-1/+1
Icount triggers don't have a maskmax field at all. This is a cut and paste error. Change-Id: I001b3d41bf683599706dba713f7be475e8dd1668 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-24target/riscv: AIA regs, check for H not VTim Newsome1-3/+3
Change-Id: Iac37b79dc737fd64a21dce83b3ef36f1a8aae118 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-23target/riscv: leaf PTE check PTE_W missingpanciyan1-1/+1
When permission bits R, W, and X in PTE all three are zero, the PTE is a pointter to the next level of the page table; otherwise, it is a leaf PTE. Here PTE_W is missed. Change-Id: I82a4cc4e64280f0fcad75b20e51b617520aff29b Signed-off-by: panciyan <panciyan@eswincomputing.com>
2023-03-22Merge pull request #818 from riscv/windows_buildopenocd64-d486b21Tim Newsome1-0/+6
Try to upload Windows binary as artifact.
2023-03-21Upload Windows binary as artifact.Tim Newsome1-0/+6
Change-Id: Iee52373a367eed61e98e828198921c9f840d9a81 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-20Merge pull request #815 from riscv/s_aiaTim Newsome5-96/+250
target/riscv: Expose S?aia CSRs if they're on the target.
2023-03-17workflow/checkpatch: Install python modules for spdxcheck.pyTim Newsome1-1/+1
Change-Id: I3be881cd57fee4cbb5a80d81562515cdec831dd6 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-17gdb_server: Keep working if gdb requests a non-existent regTim Newsome1-1/+1
Change-Id: Ica55a227f7df4f0606fa1ac071bca172411e9230 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-16Fix build.Tim Newsome3-11/+10
Change-Id: I89de7dc21d7958531ec9619905d3d8c4f54a3acf
2023-03-16Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstreamTim Newsome1587-13867/+26952
This includes https://sourceforge.net/p/openocd/mailman/message/37710818/, which should fix #814. Conflicts: .travis.yml contrib/loaders/flash/stm32/stm32f1x.S contrib/loaders/flash/stm32/stm32f2x.S doc/openocd.texi src/rtos/FreeRTOS.c src/server/gdb_server.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c src/target/riscv/riscv.h src/target/riscv/riscv_semihosting.c tcl/target/esp_common.cfg tcl/target/gd32vf103.cfg tools/scripts/checkpatch.pl Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
2023-03-16Merge pull request #800 from en-sc/en-sc/try-all-trigs-in-maybe-add-trigTim Newsome1-185/+245
Try all triggers in maybe_add_trigger_t*
2023-03-16Expose S?aia CSRs if they're on the target.Tim Newsome4-3/+88
Untested, because I don't have a target that implements this. Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-16Update encoding.h.Tim Newsome1-93/+162
Change-Id: I1b6d2cac86ec485310761b73370fb2667ebb3bbd
2023-03-15Merge pull request #812 from XuHangHub/riscvTim Newsome1-5/+5
target/riscv: fix the bug of using S2 register in read_memory_progbuf
2023-03-15Try all triggers in maybe_add_trigger_t2 and _t6Evgeniy Naydanov1-185/+245
It is possible for triggers of the same type to support different match field values, so it is needed to try all the triggers, not just the first one. Fixes issue #788. Signed-off-by: Evgeniy Naydanov evgeniy.naydanov@syntacore.com Change-Id: I4c9fbc98bae7259377456d9ad8e770232724a592
2023-03-13Merge pull request #811 from riscv/address_inTim Newsome1-2/+1
target/riscv: Remove unused address_in variable.
2023-03-12target/riscv: fix the bug of using S2 register in read_memory_progbufHang Xu1-5/+5
We should avoid using x16~x31 register in program buffer because there are no such general purpose registers in RVE(Embedded) extension. For targets that support rvE, when the parameter increment=0 and count>1 of the read_memory_progbuf function, openocd will cause an error due to the use of the s2 register. For example: {Command} {riscv repeat_read} count address [size=4] Change-Id: I8b74dcc15cd00a400f2f1354c577a82132394435 Signed-off-by: Hang Xu <xuhang@eswincomputing.com>
2023-03-10target/riscv: Remove unused address_in variable.Tim Newsome1-2/+1
Change-Id: Iead46b543a3b866f36b4d61a8824b6335dab276a Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-08Calculate the FreeRTOS type sizes and offsets more adaptively. (#806)Chao Du2-6/+55
* Calculate the FreeRTOS type sizes and offsets more adaptively. The definition of TickType_t varies between different targets. And it is also related to configUSE_16_BIT_TICKS option. Thus introduce a new command to make sure we are using a correct ticktype size. Change-Id: I9e38b331a9f07b96eb9a2c259e32377fca0106ad Signed-off-by: Chao Du <duchao@eswincomputing.com> * redundant semicolon. Change-Id: Ia21f0537e476099d8fe519ef78b3328d14123a38 * Update after review. Change-Id: I1825185ec9b0557d7e01f34a8f366661b3734aa7 * update doc Change-Id: I24b21c88b02ca3d76f1362f2545e86c068fc0ec6 --------- Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-03-07Merge pull request #807 from riscv/from_upstreamTim Newsome65-440/+7139
Merge from upstream
2023-03-06Merge branch 'riscv' into from_upstreamTim Newsome1-1/+1
Need the OpenOCD Snapshot workflow fix. Change-Id: I25f5f930b3f9e8d75cf8418c24039d6a0ebae9f6
2023-03-06Merge pull request #810 from riscv/snapshotTim Newsome1-1/+1
workflow: Use ubuntu-20.04 to build snapshot
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