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2020-06-23Accept dmstatus.version==3 (0.14)dmstatus_versionTim Newsome1-3/+5
2020-06-18Step/resume off manual hardware triggers (#486)Tim Newsome2-30/+119
2020-06-16riscv: Avoid shadowing read_csr/write_csr macros (#483)Khem Raj1-6/+6
2020-06-09Add RISC-V to README. (#482)Tim Newsome1-1/+1
2020-05-26Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issu… (#479)Tommy Murphy1-3/+22
2020-05-19Fix semihosting for multicore targets (#478)Tim Newsome5-76/+132
2020-05-18Speed up SBA block reads roughly 2x. (#477)Tim Newsome1-3/+49
2020-05-15Improvements for the HiFive1 revB (#476)Alistair Francis3-1/+3
2020-05-14Make mem2array work with 64-bit addresses. (#475)Tim Newsome1-5/+6
2020-05-06Don't cache PC, but do cache DPC. (#473)Tim Newsome1-3/+4
2020-05-06Add awareness of halt group cause. (#472)Tim Newsome3-0/+5
2020-04-21Cache accesses through riscv_[sg]et_register. (#467)Tim Newsome2-17/+75
2020-04-13Don't propagate failure to read satp in riscv_mmu() (#466)Tim Newsome1-3/+4
2020-04-10Expose FPRs as single and double for F and D. (#465)Tim Newsome1-1/+17
2020-03-27Document default values for some config options. (#461)Tim Newsome2-9/+10
2020-03-27Fix some clang static checker complaints. (#464)Tim Newsome2-17/+21
2020-03-26Use the correct thread for memory accesses. (#459)Tim Newsome5-5/+82
2020-03-26Deal with vlenb being unreadable. (#458)Tim Newsome3-3/+8
2020-03-19Add support for HiFive1 RevB board (#456)Jonathan Tinkham5-2/+30
2020-03-18Update to 1.11 privileged spec. (#455)Tim Newsome1-261/+347
2020-03-05helper: skip including sys/sysctl.h on Linux (#450)Tim Newsome1-0/+3
2020-03-05Fix address translation when high bits are set. (#453)Tim Newsome2-6/+23
2020-02-20Give control over dcsr.ebreak[msu] bits. (#451)Tim Newsome5-6/+87
2020-02-14Add support for vector register access (#448)Tim Newsome7-51/+1776
2020-01-31Update the current thread when gdb requests a step. (#444)Tim Newsome1-4/+5
2020-01-27Complain about debug version before authentication. (#441)Tim Newsome1-3/+7
2020-01-13Handle DMI busy in sba write. (#437)Tim Newsome2-55/+54
2020-01-10Don't issue extra FENCE+FENCE.i for the current hart. (#439)Jan Matyas1-0/+4
2020-01-06Upcast mask value to work with 64-bit physical (#436)Tim Newsome1-3/+7
2019-12-31Fix bugs. Do not touch SATP if there is no MMU. (#435)Hsiangkai1-3/+5
2019-12-10riscv: translate virtual address to physical address. (#425)Hsiangkai4-1/+246
2019-12-05Increase maximum number of harts (#429)bluew1-1/+1
2019-12-04Remove unused data structure. (#431)Tim Newsome2-10/+1
2019-12-04Warn about using `-rtos riscv`. (#430)Tim Newsome1-0/+7
2019-11-27Fixed write_memory_progbuf() on RV64. (#426)Jan Matyas1-1/+1
2019-11-22Fix memory access on some targets. (#428)Tim Newsome4-4/+37
2019-11-20Fix: Take into account progbuf writability. (#424)Jan Matyas1-2/+6
2019-11-15fespi: Properly support large flash devices (#421)Tim Newsome5-92/+126
2019-11-12BSCAN batch fix (#422)Greg Savin5-45/+73
2019-11-04Add support for 64-bit memory reads/writes (#419)Tim Newsome8-56/+142
2019-10-23pmpcfg[13] only exist on RV32. (#416)Tim Newsome1-0/+2
2019-10-14Merge pull request #417 from riscv/heterogeneousTim Newsome1-2/+74
2019-10-11Combine SMP group registers into one list for gdbTim Newsome1-2/+74
2019-10-09Merge pull request #413 from riscv/complianceTim Newsome1-1/+5
2019-10-03The compliance test is poorly supported.Tim Newsome1-1/+5
2019-09-30Merge pull request #411 from riscv/from_upstreamTim Newsome198-4575/+3531
2019-09-30Fix filterdiff line.Tim Newsome1-1/+1
2019-09-27Fix the build.Tim Newsome2-18/+5
2019-09-27Update libjaylink.Tim Newsome3-2/+97
2019-09-27Merge branch 'master' into from_upstreamTim Newsome194-4565/+3439
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