riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-01-04	Deal with busy status on dbus_read() request.dmi_read	Tim Newsome	1	-1/+5
2018-01-03	Comment busy behavior.	Tim Newsome	1	-0/+3
2018-01-02	Properly fix dbus_read()	Tim Newsome	1	-14/+12
2018-01-02	Update riscv-011.c	Megan Wachs	1	-2/+6
2017-12-28	In dmi_read(), ignore stale data.	Tim Newsome	1	-0/+3
2017-12-27	Merge pull request #163 from riscv/no_abort	Tim Newsome	5	-54/+77
2017-12-27	Get rid of abort() calls.	Tim Newsome	5	-54/+77
2017-12-27	Merge pull request #162 from riscv/no_abort	Tim Newsome	3	-34/+62
2017-12-26	Propagate error instead of calling abort().	Tim Newsome	3	-34/+62
2017-12-26	Merge pull request #161 from riscv/dead_code	Tim Newsome	2	-18/+0
2017-12-26	Remove unused code.	Tim Newsome	2	-18/+0
2017-12-26	Merge pull request #160 from riscv/style	Tim Newsome	16	-735/+848
2017-12-26	Conform to OpenOCD style guide.	Tim Newsome	16	-735/+848
2017-12-26	Merge pull request #159 from riscv/update	Tim Newsome	109	-906/+5299
2017-12-22	Merge branch 'master' into update	Tim Newsome	109	-906/+5299
2017-12-22	Merge pull request #156 from riscv/fespi	Tim Newsome	2	-15/+20
2017-12-21	Fix flash/run algorithm with new register names	Tim Newsome	2	-5/+8
2017-12-21	Make functions static. Free memory.	Tim Newsome	1	-10/+12
2017-12-21	Merge pull request #155 from riscv/debug_defines	Megan Wachs	1	-22/+48
2017-12-21	Merge pull request #148 from riscv/macbuild	Megan Wachs	1	-1/+1
2017-12-21	Update debug_defines to the one used with spike.	Tim Newsome	1	-22/+48
2017-12-21	Merge pull request #145 from riscv/rbb_win	Tim Newsome	3	-8/+40
2017-12-21	Merge pull request #151 from riscv/use_paren	Tim Newsome	1	-1/+1
2017-12-21	Use parens after if.	Tim Newsome	1	-1/+1
2017-12-20	config for ESPRESSObin from Globalscale Tech. Inc.	Jiri Kastner	1	-0/+7
2017-12-20	configs for Marvell Armada 3700	Jiri Kastner	3	-0/+78
2017-12-19	Merge pull request #149 from riscv/xml_registers	Tim Newsome	8	-361/+583
2017-12-19	Add `riscv expose_csrs` command.	Tim Newsome	1	-0/+110
2017-12-19	Hide supervisor registers if there is no S mode.	Tim Newsome	2	-28/+32
2017-12-19	Give FPRs ABI names.	Tim Newsome	2	-2/+67
2017-12-19	Remove some debug printfs.	Tim Newsome	1	-2/+0
2017-12-19	Avoid another assertion failure.	Tim Newsome	1	-1/+5
2017-12-19	Read misa before using it to check for extensions.	Tim Newsome	1	-1/+2
2017-12-19	Don't rely on hart count until it's correct.	Tim Newsome	1	-1/+1
2017-12-19	Remove no-longer-true comment.	Tim Newsome	1	-1/+0
2017-12-19	Simplify examine()	Tim Newsome	1	-43/+13
2017-12-19	Make priv register 8 bits.	Tim Newsome	1	-0/+1
2017-12-19	WIP xml register for 0.11.	Tim Newsome	4	-392/+290
2017-12-19	Hide unknown registers, which probably don't exist	Tim Newsome	2	-13/+21
2017-12-19	Fix register names.	Tim Newsome	5	-46/+108
2017-12-19	WIP better CSR names, and include only existing	Tim Newsome	1	-1/+32
2017-12-19	WIP. Hide FPRs if the hart doesn't support F/D.	Tim Newsome	2	-23/+31
2017-12-19	`make all` debug tests now pass.	Tim Newsome	3	-73/+106
2017-12-19	Checkpoint that seems to work.	Tim Newsome	1	-0/+30
2017-12-15	Use %ll instead of %L instead of scanf.macbuild	Tim Newsome	1	-1/+1
2017-12-14	Merge pull request #146 from riscv/scratch_ram	Tim Newsome	1	-1/+1
2017-12-14	Fix cut and paste bug.	Tim Newsome	1	-1/+1
2017-12-14	Use abstraction because Windows is not POSIX	Tim Newsome	2	-2/+13
2017-12-14	Add win32 build to travis.	Tim Newsome	1	-6/+27
2017-12-12	target: remove unused event definitions	Tomas Vanek	3	-20/+0