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-rw-r--r--tcl/target/ti_k3.cfg50
1 files changed, 16 insertions, 34 deletions
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 6c2c2e1..883197b 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -64,9 +64,6 @@ switch $_soc {
# AM654 has 1 cluster of 2 R5s cores.
set _r5_cores 2
- set _mcu_r5_cores 2
- set _main0_r5_cores 0
- set _main1_r5_cores 0
set R5_NAMES {mcu_r5.0 mcu_r5.1}
# Sysctrl power-ap unlock offsets
@@ -84,9 +81,6 @@ switch $_soc {
# AM642 has 2 cluster of 2 R5s cores.
set _r5_cores 4
- set _mcu_r5_cores 0
- set _main0_r5_cores 2
- set _main1_r5_cores 2
set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
@@ -103,9 +97,6 @@ switch $_soc {
# J721E has 3 clusters of 2 R5 cores each.
set _r5_cores 6
- set _mcu_r5_cores 2
- set _main0_r5_cores 2
- set _main1_r5_cores 2
}
j7200 {
set _CHIPNAME j7200
@@ -117,9 +108,6 @@ switch $_soc {
# J7200 has 2 clusters of 2 R5 cores each.
set _r5_cores 4
- set _mcu_r5_cores 2
- set _main0_r5_cores 2
- set _main1_r5_cores 0
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
@@ -158,6 +146,14 @@ $_TARGETNAME.sysctrl configure -event gdb-attach {
halt 1000
}
+proc _cpu_no_smp_up {} {
+ set _current_target [target current]
+ set _current_type [$_current_target cget -type]
+
+ $_current_target arp_examine
+ $_current_target $_current_type dbginit
+}
+
set _v8_smp_targets ""
for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -206,32 +202,18 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
# inactive core examination will fail - wait till startup of additional core
target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
-}
-if { $_mcu_r5_cores != 0 } {
- proc mcu_r5_up { args } {
- foreach { _core } [set args] {
- $::_TARGETNAME.mcu_r5.$_core arp_examine
- $::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit
- }
- }
-}
-
-if { $_main0_r5_cores != 0 } {
- proc main0_r5_up { args } {
- foreach { _core } [set args] {
- $::_TARGETNAME.main0_r5.$_core arp_examine
- $::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit
- }
+ $_TARGETNAME.$_r5_name configure -event gdb-attach {
+ _cpu_no_smp_up
+ # gdb-attach default rule
+ halt 1000
}
}
-if { $_main1_r5_cores != 0 } {
- proc main1_r5_up { args } {
- foreach { _core } [set args] {
- $::_TARGETNAME.main1_r5.$_core arp_examine
- $::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit
- }
+proc r5_up { args } {
+ foreach _core $args {
+ targets $_core
+ _cpu_no_smp_up
}
}