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-rw-r--r--src/target/arm7_9_common.c20
-rw-r--r--src/target/arm7tdmi.c6
-rw-r--r--src/target/arm9tdmi.c6
-rw-r--r--src/target/arm_adi_v5.c20
-rw-r--r--src/target/arm_disassembler.c2
-rw-r--r--src/target/armv4_5.c6
-rw-r--r--src/target/armv7m.c6
-rw-r--r--src/target/breakpoints.c4
-rw-r--r--src/target/cortex_m3.c2
-rw-r--r--src/target/embeddedice.c4
-rw-r--r--src/target/etm.c2
-rw-r--r--src/target/feroceon.c2
-rw-r--r--src/target/image.c8
-rw-r--r--src/target/mips_m4k.c2
-rw-r--r--src/target/target.c20
-rw-r--r--src/target/xscale.c66
16 files changed, 88 insertions, 88 deletions
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 48ba007..50b6d6a 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -263,7 +263,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
}
else if (breakpoint->type == BKPT_SOFT)
{
- if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
+ if ((retval=arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
return retval;
/* did we already set this breakpoint? */
@@ -922,7 +922,7 @@ int arm7_9_poll(target_t *target)
{
reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
uint32_t t=*((uint32_t *)reg->value);
- if (t!=0)
+ if (t != 0)
{
LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
}
@@ -1050,19 +1050,19 @@ int arm7_9_deassert_reset(target_t *target)
jtag_add_reset(0, 0);
enum reset_types jtag_reset_config = jtag_get_reset_config();
- if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+ if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
{
LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
/* set up embedded ice registers again */
if ((retval = target_examine_one(target)) != ERROR_OK)
return retval;
- if ((retval=target_poll(target))!=ERROR_OK)
+ if ((retval=target_poll(target)) != ERROR_OK)
{
return retval;
}
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
{
return retval;
}
@@ -1147,7 +1147,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
int i;
int retval;
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
return retval;
long long then=timeval_ms();
@@ -1157,7 +1157,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
break;
embeddedice_read_reg(dbg_stat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
if (debug_level>=3)
{
@@ -2576,7 +2576,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+ if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
return retval;
int little=target->endianness==TARGET_LITTLE_ENDIAN;
@@ -2677,7 +2677,7 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
if (retval==ERROR_OK)
{
uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
- if (endaddress!=(address+count*4))
+ if (endaddress != (address+count*4))
{
LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress);
retval=ERROR_FAIL;
@@ -2734,7 +2734,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
/* convert flash writing code into a buffer in target endianness */
for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
{
- if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i]))!=ERROR_OK)
+ if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK)
{
return retval;
}
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 32f1830..21fa108 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -739,13 +739,13 @@ int arm7tdmi_examine(struct target_s *target)
}
target_set_examined(target);
}
- if ((retval=embeddedice_setup(target))!=ERROR_OK)
+ if ((retval=embeddedice_setup(target)) != ERROR_OK)
return retval;
- if ((retval=arm7_9_setup(target))!=ERROR_OK)
+ if ((retval=arm7_9_setup(target)) != ERROR_OK)
return retval;
if (arm7_9->etm_ctx)
{
- if ((retval=etm_setup(target))!=ERROR_OK)
+ if ((retval=etm_setup(target)) != ERROR_OK)
return retval;
}
return ERROR_OK;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 07146c5..75ae3e8 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -831,13 +831,13 @@ int arm9tdmi_examine(struct target_s *target)
}
target_set_examined(target);
}
- if ((retval=embeddedice_setup(target))!=ERROR_OK)
+ if ((retval=embeddedice_setup(target)) != ERROR_OK)
return retval;
- if ((retval=arm7_9_setup(target))!=ERROR_OK)
+ if ((retval=arm7_9_setup(target)) != ERROR_OK)
return retval;
if (arm7_9->etm_ctx)
{
- if ((retval=etm_setup(target))!=ERROR_OK)
+ if ((retval=etm_setup(target)) != ERROR_OK)
return retval;
}
return ERROR_OK;
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index c7d3bc4..2584dbc 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -195,7 +195,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
*/
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("BUG: Why does this fail the first time????");
}
@@ -203,7 +203,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
#endif
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
swjdp->ack = swjdp->ack & 0x7;
@@ -228,7 +228,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
}
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
swjdp->ack = swjdp->ack & 0x7;
}
@@ -261,19 +261,19 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
/* Clear Sticky Error Bits */
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
}
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -971,7 +971,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
/* Check that we have debug power domains activated */
@@ -979,7 +979,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
{
LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
alive_sleep(10);
}
@@ -988,7 +988,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
{
LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
alive_sleep(10);
}
@@ -1027,7 +1027,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
swjdp_transaction_endcheck(swjdp);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
+ mem_ap = ((apid&0x10000)&&((apid&0x0F) != 0));
command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid);
if (apid)
{
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 9396ee0..90442ea 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -1435,7 +1435,7 @@ int evaluate_shift_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_
break;
}
- if ((imm==0) && (opc!=0))
+ if ((imm==0) && (opc != 0))
imm = 32;
instruction->info.data_proc.Rd = Rd;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 1817a3c..b88cdc8 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -501,9 +501,9 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t ex
}
if (target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
return retval;
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
+ if ((retval=target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
{
return retval;
}
@@ -618,7 +618,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
breakpoint_remove(target, exit_point);
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
return retval;
for (i = 0; i < num_mem_params; i++)
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index eef9b50..3e59040 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -304,9 +304,9 @@ static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, in
/* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
return retval;
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
+ if ((retval=target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
{
return retval;
}
@@ -356,7 +356,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
for (i = 0; i < num_mem_params; i++)
{
- if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value))!=ERROR_OK)
+ if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
return retval;
}
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index b1faf5a..cffe1cb 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -141,7 +141,7 @@ void breakpoint_remove(target_t *target, uint32_t address)
void breakpoint_clear_target(target_t *target)
{
breakpoint_t *breakpoint;
- while ((breakpoint = target->breakpoints)!=NULL)
+ while ((breakpoint = target->breakpoints) != NULL)
{
breakpoint_free(target, breakpoint);
}
@@ -260,7 +260,7 @@ void watchpoint_remove(target_t *target, uint32_t address)
void watchpoint_clear_target(target_t *target)
{
watchpoint_t *watchpoint;
- while ((watchpoint = target->watchpoints)!=NULL)
+ while ((watchpoint = target->watchpoints) != NULL)
{
watchpoint_free(target, watchpoint);
}
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 94fd687..644f681 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -852,7 +852,7 @@ int cortex_m3_assert_reset(target_t *target)
if (target->reset_halt)
{
int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
+ if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index acb4b61..92e322b 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -125,7 +125,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
/* identify EmbeddedICE version by reading DCC control register */
embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
{
for (i = 0; i < num_regs; i++)
{
@@ -204,7 +204,7 @@ int embeddedice_setup(target_t *target)
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
embeddedice_read_reg(dbg_ctrl);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
buf_set_u32(dbg_ctrl->value, 4, 1, 0);
embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
diff --git a/src/target/etm.c b/src/target/etm.c
index 11cb478..342ff91 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -282,7 +282,7 @@ int etm_setup(target_t *target)
buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
etm_store_reg(etm_ctrl_reg);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 0dc26dc..b9339bf 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -688,7 +688,7 @@ int feroceon_examine(struct target_s *target)
int retval;
retval = arm9tdmi_examine(target);
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
return retval;
armv4_5 = target->arch_info;
diff --git a/src/target/image.c b/src/target/image.c
index d6042e4..66bcc95 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -64,7 +64,7 @@ static int autodetect_image_type(image_t *image, char *url)
}
fileio_close(&fileio);
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
return retval;
/* check header against known signatures */
@@ -362,7 +362,7 @@ static int image_elf_read_headers(image_t *image)
return ERROR_FILEIO_OPERATION_FAILED;
}
- if (strncmp((char*)elf->header->e_ident,ELFMAG,SELFMAG)!=0)
+ if (strncmp((char*)elf->header->e_ident,ELFMAG,SELFMAG) != 0)
{
LOG_ERROR("invalid ELF file, bad magic number");
return ERROR_IMAGE_FORMAT_ERROR;
@@ -374,8 +374,8 @@ static int image_elf_read_headers(image_t *image)
}
elf->endianness = elf->header->e_ident[EI_DATA];
- if ((elf->endianness!=ELFDATA2LSB)
- &&(elf->endianness!=ELFDATA2MSB))
+ if ((elf->endianness != ELFDATA2LSB)
+ &&(elf->endianness != ELFDATA2MSB))
{
LOG_ERROR("invalid ELF file, unknown endianess setting");
return ERROR_IMAGE_FORMAT_ERROR;
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index e4259ae..f4c23d3 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -314,7 +314,7 @@ int mips_m4k_assert_reset(target_t *target)
if (target->reset_halt)
{
int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
+ if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
diff --git a/src/target/target.c b/src/target/target.c
index 7c2f8c5..5ff2232 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1088,7 +1088,7 @@ int target_arch_state(struct target_s *target)
LOG_USER("target state: %s",
Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
- if (target->state!=TARGET_HALTED)
+ if (target->state != TARGET_HALTED)
return ERROR_OK;
retval=target->type->arch_state(target);
@@ -1584,7 +1584,7 @@ static int sense_handler(void)
static int prevPowerdropout = 0;
int retval;
- if ((retval=jtag_power_dropout(&powerDropout))!=ERROR_OK)
+ if ((retval=jtag_power_dropout(&powerDropout)) != ERROR_OK)
return retval;
int powerRestored;
@@ -1603,7 +1603,7 @@ static int sense_handler(void)
lastPower = current;
}
- if ((retval=jtag_srst_asserted(&srstAsserted))!=ERROR_OK)
+ if ((retval=jtag_srst_asserted(&srstAsserted)) != ERROR_OK)
return retval;
int srstDeasserted;
@@ -1909,7 +1909,7 @@ int target_wait_state(target_t *target, enum target_state state, int ms)
for (;;)
{
- if ((retval=target_poll(target))!=ERROR_OK)
+ if ((retval=target_poll(target)) != ERROR_OK)
return retval;
if (target->state == state)
{
@@ -2872,7 +2872,7 @@ static void writeGmon(uint32_t *samples, uint32_t sampleNum, char *filename)
/*append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size) */
char *data=malloc(2*length);
- if (data!=NULL)
+ if (data != NULL)
{
for (i=0; i<length;i++)
{
@@ -2903,7 +2903,7 @@ static int handle_profile_command(struct command_context_s *cmd_ctx, char *cmd,
struct timeval timeout, now;
gettimeofday(&timeout, NULL);
- if (argc!=2)
+ if (argc != 2)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -2949,7 +2949,7 @@ static int handle_profile_command(struct command_context_s *cmd_ctx, char *cmd,
retval=ERROR_OK;
break;
}
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
{
break;
}
@@ -3388,7 +3388,7 @@ void target_handle_event( target_t *target, enum target_event e )
e,
Jim_Nvp_value2name_simple( nvp_target_event, e )->name,
Jim_GetString( teap->body, NULL ) );
- if (Jim_EvalObj( interp, teap->body )!=JIM_OK)
+ if (Jim_EvalObj( interp, teap->body ) != JIM_OK)
{
Jim_PrintErrorMessage(interp);
}
@@ -4386,7 +4386,7 @@ static struct FastLoad *fastload;
static void free_fastload(void)
{
- if (fastload!=NULL)
+ if (fastload != NULL)
{
int i;
for (i=0; i<fastload_num; i++)
@@ -4504,7 +4504,7 @@ static int handle_fast_load_image_command(struct command_context_s *cmd_ctx, cha
image_close(&image);
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
{
free_fastload();
}
diff --git a/src/target/xscale.c b/src/target/xscale.c
index e9c1d54..7de1d84 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -889,7 +889,7 @@ int xscale_update_vectors(target_t *target)
retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
{
/* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
@@ -908,7 +908,7 @@ int xscale_update_vectors(target_t *target)
retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
- if (retval!=ERROR_OK)
+ if (retval != ERROR_OK)
{
/* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
@@ -1028,11 +1028,11 @@ int xscale_debug_entry(target_t *target)
/* clear external dbg break (will be written on next DCSR read) */
xscale->external_debug_break = 0;
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
/* get r0, pc, r1 to r7 and cpsr */
- if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
+ if ((retval=xscale_receive(target, buffer, 10)) != ERROR_OK)
return retval;
/* move r0 from buffer to register cache */
@@ -1253,7 +1253,7 @@ int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
}
}
- if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1))!=ERROR_OK)
+ if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
return retval;
return ERROR_OK;
@@ -1266,7 +1266,7 @@ int xscale_disable_single_step(struct target_s *target)
reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
- if ((retval=xscale_set_reg_u32(ibcr0, 0x0))!=ERROR_OK)
+ if ((retval=xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
return retval;
return ERROR_OK;
@@ -1297,7 +1297,7 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha
}
/* update vector tables */
- if ((retval=xscale_update_vectors(target))!=ERROR_OK)
+ if ((retval=xscale_update_vectors(target)) != ERROR_OK)
return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
@@ -1451,56 +1451,56 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr
}
LOG_DEBUG("enable single-step");
- if ((retval=xscale_enable_single_step(target, next_pc))!=ERROR_OK)
+ if ((retval=xscale_enable_single_step(target, next_pc)) != ERROR_OK)
return retval;
/* restore banked registers */
- if ((retval=xscale_restore_context(target))!=ERROR_OK)
+ if ((retval=xscale_restore_context(target)) != ERROR_OK)
return retval;
/* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */
if (xscale->trace.buffer_enabled)
{
- if ((retval=xscale_send_u32(target, 0x62))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x62)) != ERROR_OK)
return retval;
- if ((retval=xscale_send_u32(target, 0x31))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x31)) != ERROR_OK)
return retval;
}
else
- if ((retval=xscale_send_u32(target, 0x30))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x30)) != ERROR_OK)
return retval;
/* send CPSR */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
for (i = 7; i >= 0; i--)
{
/* send register */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
- if ((retval=armv4_5_invalidate_core_regs(target))!=ERROR_OK)
+ if ((retval=armv4_5_invalidate_core_regs(target)) != ERROR_OK)
return retval;
/* wait for and process debug entry */
- if ((retval=xscale_debug_entry(target))!=ERROR_OK)
+ if ((retval=xscale_debug_entry(target)) != ERROR_OK)
return retval;
LOG_DEBUG("disable single-step");
- if ((retval=xscale_disable_single_step(target))!=ERROR_OK)
+ if ((retval=xscale_disable_single_step(target)) != ERROR_OK)
return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -1531,7 +1531,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand
/* if we're at the reset vector, we have to simulate the step */
if (current_pc == 0x0)
{
- if ((retval=arm_simulate_step(target, NULL))!=ERROR_OK)
+ if ((retval=arm_simulate_step(target, NULL)) != ERROR_OK)
return retval;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
@@ -1545,7 +1545,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
- if ((retval=xscale_unset_breakpoint(target, breakpoint))!=ERROR_OK)
+ if ((retval=xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
return retval;
}
@@ -1597,7 +1597,7 @@ int xscale_assert_reset(target_t *target)
if (target->reset_halt)
{
int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
+ if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
@@ -1930,20 +1930,20 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size,
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory read request (command 0x1n, n: access size) */
- if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
return retval;
/* send base address for read request */
- if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, address)) != ERROR_OK)
return retval;
/* send number of requested data words */
- if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, count)) != ERROR_OK)
return retval;
/* receive data from target (count times 32-bit words in host endianness) */
buf32 = malloc(4 * count);
- if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
+ if ((retval=xscale_receive(target, buf32, count)) != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
@@ -1971,12 +1971,12 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size,
free(buf32);
/* examine DCSR, to see if Sticky Abort (SA) got set */
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
@@ -2007,15 +2007,15 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory write request (command 0x2n, n: access size) */
- if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
return retval;
/* send base address for read request */
- if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, address)) != ERROR_OK)
return retval;
/* send number of requested data words to be written*/
- if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, count)) != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
@@ -2045,16 +2045,16 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size
}
}
#endif
- if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
+ if ((retval=xscale_send(target, buffer, count, size)) != ERROR_OK)
return retval;
/* examine DCSR, to see if Sticky Abort (SA) got set */
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
generated by cgit v1.1 at 2024-11-07 02:25:05 +0000