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-rw-r--r--src/target/startup.tcl13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 75e0edc..8ddac0c 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -131,6 +131,11 @@ proc ocd_process_reset_inner { MODE } {
}
}
+ # no need to wait for a target that is unavailable anyway
+ if { [$t curstate] == "unavailable" } {
+ continue
+ }
+
# Wait up to 1 second for target to halt. Why 1sec? Cause
# the JTAG tap reset signal might be hooked to a slow
# resistor/capacitor circuit - and it might take a while
@@ -142,8 +147,11 @@ proc ocd_process_reset_inner { MODE } {
# Did we succeed?
set s [$t curstate]
+ if { $s == "unavailable" } {
+ continue
+ }
if { $s != "halted" } {
- return -code error [format "TARGET: %s - Not halted" $t]
+ return -code error [format "TARGET: %s - Not halted (%s)" $t $s]
}
}
}
@@ -160,6 +168,9 @@ proc ocd_process_reset_inner { MODE } {
if { ![$t was_examined] && [$t examine_deferred] } {
continue
}
+ if { [$t curstate] == "unavailable" } {
+ continue
+ }
set err [catch "$t arp_waitstate halted 5000"]
# Did it halt?