diff options
| -rw-r--r-- | tcl/target/nrf52.cfg | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg index a9121d3..0703b18 100644 --- a/tcl/target/nrf52.cfg +++ b/tcl/target/nrf52.cfg @@ -131,6 +131,26 @@ proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} { 0x52840 - 0x52833 - 0x52832 { + # Configuration values for all supported trace port speeds, see + # TRACECONFIG.TRACEPORTSPEED + set trace_port_speeds { + 32000000 0 + 16000000 1 + 8000000 2 + 4000000 3 + } + + # Note that trace port clock stands for what is referred to as + # TRACECLKIN in the Arm CoreSight documentation. + set trace_port_clock [$_chipname.tpiu cget -traceclk] + + if { ![dict exists $trace_port_speeds $trace_port_clock] } { + error "Trace clock speed is not supported" + } + + # Set TRACECONFIG.TRACEPORTSPEED + mmw 0x4000055C [dict get $trace_port_speeds $trace_port_clock] 0x3 + if { [$_chipname.tpiu cget -protocol] eq "sync" } { if { [$_chipname.tpiu cget -port-width] != 4 } { error "Device only supports 4-bit sync traces" |