diff options
| -rw-r--r-- | tcl/target/rp2040-core0.cfg | 12 | ||||
| -rw-r--r-- | tcl/target/rp2040.cfg | 74 |
2 files changed, 86 insertions, 0 deletions
diff --git a/tcl/target/rp2040-core0.cfg b/tcl/target/rp2040-core0.cfg index 6a0f0ed..8a111bc 100644 --- a/tcl/target/rp2040-core0.cfg +++ b/tcl/target/rp2040-core0.cfg @@ -1,5 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-or-later +# RP2040 is a microcontroller with dual Cortex-M0+ core. +# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html + +# The device requires multidrop SWD for debug. +# This configuration file is intended for a special adapter +# which selects a multidrop target on its own. +# Cannot be used with a standard SWD adapter! + +echo "Warn : rp2040-core0.cfg configuration file is deprecated and will be" +echo " removed in the next release. Use following parameters instead:" +echo " -c 'set USE_CORE 0' -f target/rp2040.cfg" + transport select swd source [find target/swj-dp.tcl] diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg new file mode 100644 index 0000000..ee45542 --- /dev/null +++ b/tcl/target/rp2040.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# RP2040 is a microcontroller with dual Cortex-M0+ core. +# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html + +# The device requires multidrop SWD for debug. +transport select swd + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rp2040 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x01002927 +} + +# Set to '0' or '1' for single core configuration, +# anything else for isolated debugging of both cores +if { [info exists USE_CORE] } { + set _USE_CORE $USE_CORE +} else { + set _USE_CORE { 0 1 } +} +set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }] + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +# core 0 +if { $_USE_CORE != 1 } { + dap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0 + set _TARGETNAME_0 $_CHIPNAME.core0 + target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0 + # srst does not exist; use SYSRESETREQ to perform a soft reset + $_TARGETNAME_0 cortex_m reset_config sysresetreq +} + +# core 1 +if { $_USE_CORE != 0 } { + dap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1 + set _TARGETNAME_1 $_CHIPNAME.core1 + target create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1 + $_TARGETNAME_1 cortex_m reset_config sysresetreq +} + +if { $_USE_CORE == 1 } { + set _FLASH_TARGET $_TARGETNAME_1 +} else { + set _FLASH_TARGET $_TARGETNAME_0 +} +# Backup the work area. The flash probe runs an algorithm on the target CPU. +# The flash is probed during gdb connect if gdb_memory_map is enabled (by default). +$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET + +if { $_BOTH_CORES } { + # Alias to ensure gdb connecting to core 1 gets the correct memory map + flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME + + # Select core 0 + targets $_TARGETNAME_0 +} |