diff options
45 files changed, 66 insertions, 66 deletions
@@ -77,7 +77,7 @@ This is always a 32bit hex number. Examples: 0x1f0f0f0f - is an old ARM7TDMI 0x3f0f0f0f - is a newer ARM7TDMI - 0x3ba00477 - is an ARM cortex M3 + 0x3ba00477 - is an ARM Cortex-M3 Some chips have multiple JTAG taps - be sure to list each one individually - ORDER is important! @@ -170,9 +170,9 @@ https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html garabage. - implement missing functionality (grep FNC_INFO_NOTIMPLEMENTED ...) - Thumb2 single stepping: ARM1156T2 needs simulator support -- Cortex A8 support (ML) +- Cortex-A8 support (ML) - add target implementation (ML) -- Cortex M3 support +- Cortex-M3 support - when stepping, only write dirtied registers (be faster) - when connecting to halted core, fetch registers (startup is quirky) - Generic ARM run_algorithm() interface diff --git a/contrib/loaders/flash/cortex-m0.S b/contrib/loaders/flash/cortex-m0.S index a905a36..b4416e7 100644 --- a/contrib/loaders/flash/cortex-m0.S +++ b/contrib/loaders/flash/cortex-m0.S @@ -27,8 +27,8 @@ /* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is * very generic (CPU blocks during flash writes), so this is actually - * just a generic word-oriented copy routine for cortex-m0 (also - * suitable for cortex m0plus/m3/m4.) + * just a generic word-oriented copy routine for Cortex-M0 (also + * suitable for Cortex-M0+/M3/M4.) * * To assemble: * arm-none-eabi-gcc -c cortex-m0.S diff --git a/doc/openocd.texi b/doc/openocd.texi index 3e249c0..ae92697 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -995,7 +995,7 @@ For example, there may be configuration files for your JTAG adapter and target chip, but you need a new board-specific config file giving access to your particular flash chips. Or you might need to write another target chip configuration file -for a new chip built around the Cortex M3 core. +for a new chip built around the Cortex-M3 core. @quotation Note When you write new configuration files, please submit @@ -5215,7 +5215,7 @@ The AVR 8-bit microcontrollers from Atmel integrate flash memory. @deffn {Flash Driver} efm32 All members of the EFM32 microcontroller family from Energy Micro include -internal flash and use ARM Cortex M3 cores. The driver automatically recognizes +internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. @example @@ -5235,7 +5235,7 @@ supported.} @deffn {Flash Driver} fm3 All members of the FM3 microcontroller family from Fujitsu -include internal flash and use ARM Cortex M3 cores. +include internal flash and use ARM Cortex-M3 cores. The @var{fm3} driver uses the @var{target} parameter to select the correct bank config, it can currently be one of the following: @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu}, @@ -5267,7 +5267,7 @@ nor is Chip Erase (only Sector Erase is implemented).} @deffn {Flash Driver} kinetis @cindex kinetis Kx and KLx members of the Kinetis microcontroller family from Freescale include -internal flash and use ARM Cortex M0+ or M4 cores. The driver automatically +internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically recognizes flash size and a number of flash banks (1-4) using the chip identification register, and autoconfigures itself. @@ -5325,7 +5325,7 @@ Command disables watchdog timer. @deffn {Flash Driver} kinetis_ke @cindex kinetis_ke KE members of the Kinetis microcontroller family from Freescale include -internal flash and use ARM Cortex M0+. The driver automatically recognizes +internal flash and use ARM Cortex-M0+. The driver automatically recognizes the KE family and sub-family using the chip identification register, and autoconfigures itself. @@ -5686,7 +5686,7 @@ This will remove any Code Protection. @deffn {Flash Driver} psoc4 All members of the PSoC 41xx/42xx microcontroller family from Cypress -include internal flash and use ARM Cortex M0 cores. +include internal flash and use ARM Cortex-M0 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. @@ -5720,7 +5720,7 @@ The @var{num} parameter is a value shown by @command{flash banks}. @deffn {Flash Driver} sim3x All members of the SiM3 microcontroller family from Silicon Laboratories -include internal flash and use ARM Cortex M3 cores. It supports both JTAG +include internal flash and use ARM Cortex-M3 cores. It supports both JTAG and SWD interface. The @var{sim3x} driver tries to probe the device to auto detect the MCU. If this failes, it will use the @var{size} parameter as the size of flash bank. diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index 9d119bb..9782fd8 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -2482,7 +2482,7 @@ static const char *const eproc_names[] = { _unknown, /* 0 */ "arm946es", /* 1 */ "arm7tdmi", /* 2 */ - "cortex-m3", /* 3 */ + "Cortex-M3", /* 3 */ "arm920t", /* 4 */ "arm926ejs", /* 5 */ _unknown, /* 6 */ diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index 88ff6d7..bcaaaa0 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -1407,11 +1407,11 @@ static const char *const eproc_names[] = { _unknown, /* 0 */ "arm946es", /* 1 */ "arm7tdmi", /* 2 */ - "cortex-m3", /* 3 */ + "Cortex-M3", /* 3 */ "arm920t", /* 4 */ "arm926ejs", /* 5 */ - "cortex-a5", /* 6 */ - "cortex-m4", /* 7 */ + "Cortex-A5", /* 6 */ + "Cortex-M4", /* 7 */ _unknown, /* 8 */ _unknown, /* 9 */ _unknown, /* 10 */ diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c index 08f8bb8..77fb7e6 100644 --- a/src/flash/nor/atsamv.c +++ b/src/flash/nor/atsamv.c @@ -355,7 +355,7 @@ static int samv_probe(struct flash_bank *bank) uint8_t eproc = (device_id >> 5) & 0x7; if (eproc != 0) { - LOG_ERROR("unexpected eproc code: %d was expecting 0 (cortex-m7)", eproc); + LOG_ERROR("unexpected eproc code: %d was expecting 0 (Cortex-M7)", eproc); return ERROR_FAIL; } diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c index ab543d6..5627a62 100644 --- a/src/flash/nor/efm32.c +++ b/src/flash/nor/efm32.c @@ -144,11 +144,11 @@ static int efm32x_read_info(struct flash_bank *bank, return ret; if (((cpuid >> 4) & 0xfff) == 0xc23) { - /* Cortex M3 device */ + /* Cortex-M3 device */ } else if (((cpuid >> 4) & 0xfff) == 0xc24) { - /* Cortex M4 device(WONDER GECKO) */ + /* Cortex-M4 device (WONDER GECKO) */ } else if (((cpuid >> 4) & 0xfff) == 0xc60) { - /* Cortex M0plus device */ + /* Cortex-M0+ device */ } else { LOG_ERROR("Target is not Cortex-Mx Device"); return ERROR_FAIL; diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c index 9e32c01..ff72ea0 100644 --- a/src/flash/nor/niietcm4.c +++ b/src/flash/nor/niietcm4.c @@ -1719,7 +1719,7 @@ static int niietcm4_auto_probe(struct flash_bank *bank) static int get_niietcm4_info(struct flash_bank *bank, char *buf, int buf_size) { struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv; - LOG_INFO("\nNIIET Cortex M4F %s\n%s", niietcm4_info->chip_name, niietcm4_info->chip_brief); + LOG_INFO("\nNIIET Cortex-M4F %s\n%s", niietcm4_info->chip_name, niietcm4_info->chip_brief); snprintf(buf, buf_size, " "); return ERROR_OK; diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c index df4e19c..bb1743e 100644 --- a/src/flash/nor/sim3x.c +++ b/src/flash/nor/sim3x.c @@ -748,7 +748,7 @@ static int sim3x_read_info(struct flash_bank *bank) } if (((cpuid >> 4) & 0xfff) != 0xc23) { - LOG_ERROR("Target is not CortexM3"); + LOG_ERROR("Target is not Cortex-M3"); return ERROR_FAIL; } @@ -1009,7 +1009,7 @@ COMMAND_HANDLER(sim3x_lock) return ret; if ((val & CPUID_CHECK_VALUE_MASK) != CPUID_CHECK_VALUE) { - LOG_ERROR("Target is not ARM CortexM3 or is already locked"); + LOG_ERROR("Target is not ARM Cortex-M3 or is already locked"); return ERROR_FAIL; } } else { diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c index 904ab40..3d14f6d 100644 --- a/src/jtag/drivers/openjtag.c +++ b/src/jtag/drivers/openjtag.c @@ -32,7 +32,7 @@ ***************************************************************************/ /*************************************************************************** - * Version 1.0 Tested on a MCBSTM32 board using a Cortex M3 (stm32f103x), * + * Version 1.0 Tested on a MCBSTM32 board using a Cortex-M3 (stm32f103x), * * GDB and Eclipse under Linux (Ubuntu 10.04) * * * ***************************************************************************/ diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c index 649368d..bbd31d8 100644 --- a/src/jtag/drivers/stlink_usb.c +++ b/src/jtag/drivers/stlink_usb.c @@ -1164,7 +1164,7 @@ static int stlink_usb_step(void *handle) if (h->jtag_api == STLINK_JTAG_API_V2) { /* TODO: this emulates the v1 api, it should really use a similar auto mask isr - * that the cortex-m3 currently does. */ + * that the Cortex-M3 currently does. */ stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_HALT|C_MASKINTS|C_DEBUGEN); stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_STEP|C_MASKINTS|C_DEBUGEN); return stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_HALT|C_DEBUGEN); diff --git a/src/rtos/ChibiOS.c b/src/rtos/ChibiOS.c index 8439386..be91be5 100644 --- a/src/rtos/ChibiOS.c +++ b/src/rtos/ChibiOS.c @@ -226,7 +226,7 @@ static int ChibiOS_update_stacking(struct rtos *rtos) /* Sometimes the stacking can not be determined only by looking at the * target name but only a runtime. * - * For example, this is the case for cortex-m4 targets and ChibiOS which + * For example, this is the case for Cortex-M4 targets and ChibiOS which * only stack the FPU registers if it is enabled during ChibiOS build. * * Terminating which stacking is used is target depending. @@ -248,7 +248,7 @@ static int ChibiOS_update_stacking(struct rtos *rtos) struct ChibiOS_params *param; param = (struct ChibiOS_params *) rtos->rtos_specific_params; - /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4 */ + /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4 */ struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); if (is_armv7m(armv7m_target)) { if (armv7m_target->fp_feature == FPv4_SP) { diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c index 9313773..a58eed1 100644 --- a/src/rtos/FreeRTOS.c +++ b/src/rtos/FreeRTOS.c @@ -430,7 +430,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, ch thread_id + param->thread_stack_offset, stack_ptr); - /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4F */ + /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4F */ int cm4_fpu_enabled = 0; struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); if (is_armv7m(armv7m_target)) { diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c index 272658c..f0f419c 100644 --- a/src/rtos/mqx.c +++ b/src/rtos/mqx.c @@ -109,7 +109,7 @@ static int mqx_valid_address_check( enum mqx_arch arch_type = ((struct mqx_params *)rtos->rtos_specific_params)->target_arch; const char * targetname = ((struct mqx_params *)rtos->rtos_specific_params)->target_name; - /* Cortex M address range */ + /* Cortex-M address range */ if (arch_type == mqx_arch_cortexm) { if ( /* code and sram area */ diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c index 7d72b4e..32f82a9 100644 --- a/src/rtos/rtos_standard_stackings.c +++ b/src/rtos/rtos_standard_stackings.c @@ -182,7 +182,7 @@ int64_t rtos_generic_stack_align8(struct target *target, stacking, stack_ptr, 8); } -/* The Cortex M3 will indicate that an alignment adjustment +/* The Cortex-M3 will indicate that an alignment adjustment * has been done on the stack by setting bit 9 of the stacked xPSR * register. In this case, we can just add an extra 4 bytes to get * to the program stack. Note that some places in the ARM documentation diff --git a/src/target/armv7a.c b/src/target/armv7a.c index b9320d1..6dbe10d 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -177,7 +177,7 @@ done: return retval; } -/* method adapted to cortex A : reused arm v4 v5 method*/ +/* method adapted to Cortex-A : reused ARM v4 v5 method */ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val) { uint32_t first_lvl_descriptor = 0x0; diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index a97e594..b345dfc 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -18,7 +18,7 @@ * michel.jaouen@stericsson.com : smp minimum support * * * * Copyright (C) Broadcom 2012 * - * ehunter@broadcom.com : Cortex R4 support * + * ehunter@broadcom.com : Cortex-R4 support * * * * Copyright (C) 2013 Kamal Dasu * * kdasu.kdev@gmail.com * @@ -2664,7 +2664,7 @@ out: /* * Cortex-A Memory access * - * This is same Cortex M3 but we must also use the correct + * This is same Cortex-M3 but we must also use the correct * ap number for every access. */ diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 32b46d3..29f0cdd 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1932,7 +1932,7 @@ int cortex_m_examine(struct target *target) } LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); - /* test for floating point feature on cortex-m4 */ + /* test for floating point feature on Cortex-M4 */ if (i == 4) { target_read_u32(target, MVFR0, &mvfr0); target_read_u32(target, MVFR1, &mvfr1); diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg index fccf8c5..25fe1f4 100644 --- a/tcl/target/altera_fpgasoc.cfg +++ b/tcl/target/altera_fpgasoc.cfg @@ -27,7 +27,7 @@ jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected- # -# Cortex A9 target +# Cortex-A9 target # # GDB target: Cortex-A9, using DAP, configuring only one core @@ -59,6 +59,6 @@ $_TARGETNAME1 configure -event gdb-attach { halt } #$_TARGETNAME2 configure -event gdb-attach { halt } proc cycv_dbginit {target} { - # General Cortex A8/A9 debug initialisation + # General Cortex-A8/A9 debug initialisation cortex_a dbginit } diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg index ce7cfb6..7409615 100644 --- a/tcl/target/am335x.cfg +++ b/tcl/target/am335x.cfg @@ -63,13 +63,13 @@ proc enable_default_taps { taps } { } # -# Cortex M3 target +# Cortex-M3 target # set _TARGETNAME_2 $_CHIPNAME.m3 target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap # -# Cortex A8 target +# Cortex-A8 target # set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000 diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg index 4f97f81..fe0ffff 100644 --- a/tcl/target/am437x.cfg +++ b/tcl/target/am437x.cfg @@ -484,7 +484,7 @@ jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME" jtag configure $JRC_NAME -event post-reset "runtest 100" # -# Cortex A9 target +# Cortex-A9 target # target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000 diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg index 59fbbf0..c00dae9 100644 --- a/tcl/target/amdm37x.cfg +++ b/tcl/target/amdm37x.cfg @@ -199,7 +199,7 @@ $_TARGETNAME configure -event gdb-attach { # Run this to enable invasive debugging. This is run automatically in the # reset sequence. proc amdm37x_dbginit {target} { - # General Cortex A8 debug initialisation + # General Cortex-A8 debug initialisation cortex_a dbginit # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg index 6af1f5c..fca655d 100644 --- a/tcl/target/at91sam3XXX.cfg +++ b/tcl/target/at91sam3XXX.cfg @@ -1,4 +1,4 @@ -# script for ATMEL sam3, a CORTEX-M3 chip +# script for ATMEL sam3, a Cortex-M3 chip # # at91sam3u4e # at91sam3u2e diff --git a/tcl/target/at91sam3ax_xx.cfg b/tcl/target/at91sam3ax_xx.cfg index 8e6bc33..e561771 100644 --- a/tcl/target/at91sam3ax_xx.cfg +++ b/tcl/target/at91sam3ax_xx.cfg @@ -1,4 +1,4 @@ -# script for ATMEL sam3, a CORTEX-M3 chip +# script for ATMEL sam3, a Cortex-M3 chip # # at91sam3A4C # at91sam3A8C diff --git a/tcl/target/at91sam3sXX.cfg b/tcl/target/at91sam3sXX.cfg index ca7092b..09146bd 100644 --- a/tcl/target/at91sam3sXX.cfg +++ b/tcl/target/at91sam3sXX.cfg @@ -1,4 +1,4 @@ -# script for ATMEL sam3, a CORTEX-M3 chip +# script for ATMEL sam3, a Cortex-M3 chip # # at91sam3s4c # at91sam3s4b diff --git a/tcl/target/at91sam3uxx.cfg b/tcl/target/at91sam3uxx.cfg index a11afc0..b42ae19 100644 --- a/tcl/target/at91sam3uxx.cfg +++ b/tcl/target/at91sam3uxx.cfg @@ -1,4 +1,4 @@ -# script for ATMEL sam3, a CORTEX-M3 chip +# script for ATMEL sam3, a Cortex-M3 chip # # at91sam3u4e # at91sam3u2e diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg index 8f32ca0..ca80143 100644 --- a/tcl/target/at91sam4XXX.cfg +++ b/tcl/target/at91sam4XXX.cfg @@ -1,5 +1,5 @@ # -# script for ATMEL sam4, a CORTEX-M4 chip +# script for ATMEL sam4, a Cortex-M4 chip # # diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg index 46c38ae..4aee7d0 100644 --- a/tcl/target/at91sam4lXX.cfg +++ b/tcl/target/at91sam4lXX.cfg @@ -1,4 +1,4 @@ -# script for ATMEL sam4l, a CORTEX-M4 chip +# script for ATMEL sam4l, a Cortex-M4 chip # source [find target/at91sam4XXX.cfg] diff --git a/tcl/target/at91sam4sXX.cfg b/tcl/target/at91sam4sXX.cfg index 3de4aa8..8883e23 100644 --- a/tcl/target/at91sam4sXX.cfg +++ b/tcl/target/at91sam4sXX.cfg @@ -1,4 +1,4 @@ -# script for ATMEL sam4, a CORTEX-M4 chip +# script for ATMEL sam4, a Cortex-M4 chip # source [find target/at91sam4XXX.cfg] diff --git a/tcl/target/at91sam4sd32x.cfg b/tcl/target/at91sam4sd32x.cfg index e44db66..077b1f5 100644 --- a/tcl/target/at91sam4sd32x.cfg +++ b/tcl/target/at91sam4sd32x.cfg @@ -1,4 +1,4 @@ -# script for ATMEL sam4sd32, a CORTEX-M4 chip +# script for ATMEL sam4sd32, a Cortex-M4 chip # source [find target/at91sam4XXX.cfg] diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg index 50d93f5..47b4f5f 100644 --- a/tcl/target/at91samdXX.cfg +++ b/tcl/target/at91samdXX.cfg @@ -1,5 +1,5 @@ # -# script for Atmel SAMD, SAMR, SAML or SAMC, a CORTEX-M0 chip +# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip # # diff --git a/tcl/target/at91samg5x.cfg b/tcl/target/at91samg5x.cfg index d26455b..57274c0 100644 --- a/tcl/target/at91samg5x.cfg +++ b/tcl/target/at91samg5x.cfg @@ -1,4 +1,4 @@ -# script for the ATMEL samg5x CORTEX-M4F chip family +# script for the ATMEL samg5x Cortex-M4F chip family # source [find target/at91sam4XXX.cfg] diff --git a/tcl/target/bcm281xx.cfg b/tcl/target/bcm281xx.cfg index c05682f..224af79 100644 --- a/tcl/target/bcm281xx.cfg +++ b/tcl/target/bcm281xx.cfg @@ -17,7 +17,7 @@ if { [info exists DAP_TAPID] } { jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4 -# Dual Cortex A9s +# Dual Cortex-A9 set _TARGETNAME0 $_CHIPNAME.cpu0 set _TARGETNAME1 $_CHIPNAME.cpu1 diff --git a/tcl/target/cc26xx.cfg b/tcl/target/cc26xx.cfg index 0fa4600..1492e6a 100755 --- a/tcl/target/cc26xx.cfg +++ b/tcl/target/cc26xx.cfg @@ -37,7 +37,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc" # -# Cortex M3 target +# Cortex-M3 target # set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap diff --git a/tcl/target/cc32xx.cfg b/tcl/target/cc32xx.cfg index ff65450..154bf91 100755 --- a/tcl/target/cc32xx.cfg +++ b/tcl/target/cc32xx.cfg @@ -47,7 +47,7 @@ if {[using_jtag]} { } # -# Cortex M3 target +# Cortex-M3 target # set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg index e2d78d1..78bbc94 100644 --- a/tcl/target/fm3.cfg +++ b/tcl/target/fm3.cfg @@ -27,7 +27,7 @@ if {[using_jtag]} { jtag_ntrst_delay 100 } -# Fujitsu cortex-M3 reset configuration +# Fujitsu Cortex-M3 reset configuration reset_config trst_only swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg index 15d5c04..b143aad 100644 --- a/tcl/target/imx51.cfg +++ b/tcl/target/imx51.cfg @@ -40,7 +40,7 @@ jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100" jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP" proc imx51_dbginit {target} { - # General Cortex A8 debug initialisation + # General Cortex-A8 debug initialisation cortex_a dbginit } diff --git a/tcl/target/imx53.cfg b/tcl/target/imx53.cfg index e77bc34..87a3008 100644 --- a/tcl/target/imx53.cfg +++ b/tcl/target/imx53.cfg @@ -40,7 +40,7 @@ jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100" jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP" proc imx53_dbginit {target} { - # General Cortex A8 debug initialisation + # General Cortex-A8 debug initialisation cortex_a dbginit } diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg index 11c2134..4f7e98a 100644 --- a/tcl/target/imx6.cfg +++ b/tcl/target/imx6.cfg @@ -47,7 +47,7 @@ target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" proc imx6_dbginit {target} { - # General Cortex A8/A9 debug initialisation + # General Cortex-A8/A9 debug initialisation cortex_a dbginit } diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg index 226425d..9c10e9f 100644 --- a/tcl/target/lpc1xxx.cfg +++ b/tcl/target/lpc1xxx.cfg @@ -56,7 +56,7 @@ if { [info exists CPUTAPID] } { # Allow user override set _CPUTAPID $CPUTAPID } else { - # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core. + # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core. if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } { set _CPUTAPID 0x0bb11477 } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { @@ -148,10 +148,10 @@ if {[using_jtag]} { jtag_ntrst_delay 200 } -# LPC8xx (Cortex M0+ core) support SYSRESETREQ -# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ -# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ -# LPC40xx (Cortex M4F core) support SYSRESETREQ +# LPC8xx (Cortex-M0+ core) support SYSRESETREQ +# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ +# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ +# LPC40xx (Cortex-M4F core) support SYSRESETREQ if {![using_hla]} { # if srst is not fitted use SYSRESETREQ to # perform a soft reset diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg index 0768120..280dd4f 100644 --- a/tcl/target/nrf51.cfg +++ b/tcl/target/nrf51.cfg @@ -1,5 +1,5 @@ # -# script for Nordic nRF51 series, a CORTEX-M0 chip +# script for Nordic nRF51 series, a Cortex-M0 chip # source [find target/swj-dp.tcl] diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg index f9dcf7c..c2929d1 100644 --- a/tcl/target/omap3530.cfg +++ b/tcl/target/omap3530.cfg @@ -53,7 +53,7 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" proc omap3_dbginit {target} { - # General Cortex A8 debug initialisation + # General Cortex-A8 debug initialisation cortex_a dbginit # Enable DBGU signal for OMAP353x $target mww phys 0x5401d030 0x00002000 diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg index 1a19135..d07afc4 100644 --- a/tcl/target/stm32w108xx.cfg +++ b/tcl/target/stm32w108xx.cfg @@ -1,7 +1,7 @@ # # Target configuration for the ST STM32W108xx chips # -# Processor: ARM Cortex M3 +# Processor: ARM Cortex-M3 # Date: 2013-06-09 # Author: Giuseppe Barba <giuseppe.barba@gmail.com> diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg index 582a4bf..21da6c0 100644 --- a/tcl/target/ti_tms570.cfg +++ b/tcl/target/ti_tms570.cfg @@ -53,7 +53,7 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" -# Cortex R4 target +# Cortex-R4 target set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \ -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003 |