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| author | Tomas Vanek <vanekt@fbl.cz> | 2021-11-16 12:23:48 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2022-04-24 08:26:08 +0000 |
| commit | f2b4897773a1c9db185dfb61d474055559fd507a (patch) | |
| tree | 6793b031e3173502fca50d4b3619ceaab3af51d8 /tcl | |
| parent | a26ee5344cf70e068265ac2f03a2915fae070e14 (diff) | |
| download | riscv-openocd-f2b4897773a1c9db185dfb61d474055559fd507a.zip riscv-openocd-f2b4897773a1c9db185dfb61d474055559fd507a.tar.gz riscv-openocd-f2b4897773a1c9db185dfb61d474055559fd507a.tar.bz2 | |
flash/stm32f1x: add support for RISC-V GigaDevice GD32VF103
The device has compatible flash macro with STM32F1 family, reuse
stm32f1x driver code.
Detect non-ARM target - for simplicy test target type name 'riscv'
and the address has 32 bits.
In case of RISC-V CPU use simple chunked write algo - async algo
cannot be used as the core implemented in this device doesn't
allow memory access while running.
Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6704
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Diffstat (limited to 'tcl')
0 files changed, 0 insertions, 0 deletions