diff options
author | Spencer Oliver <spen@spen-soft.co.uk> | 2012-03-26 14:54:24 +0100 |
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committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-03-30 16:02:14 +0000 |
commit | e9976aa3a879ac45dc79a96f6a87cc9fcdf7aaca (patch) | |
tree | 085ce93f023b798580a21338c5b375ed2b4bd5ce /tcl | |
parent | 4e31b8794319127851ff98a0bc271b394baf921f (diff) | |
download | riscv-openocd-e9976aa3a879ac45dc79a96f6a87cc9fcdf7aaca.zip riscv-openocd-e9976aa3a879ac45dc79a96f6a87cc9fcdf7aaca.tar.gz riscv-openocd-e9976aa3a879ac45dc79a96f6a87cc9fcdf7aaca.tar.bz2 |
cfg: add STM32F4x and STM3241G-EVAL config files
This adds support for the STM32F4 target and the STM3241G Eval Board, in
both standalone and using the onboard STLINK.
Change-Id: I62f8908b5880568b2b36c78a78f94c40861ff335
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/540
Tested-by: jenkins
Diffstat (limited to 'tcl')
-rw-r--r-- | tcl/board/stm3241g_eval.cfg | 11 | ||||
-rw-r--r-- | tcl/board/stm3241g_eval_stlink.cfg | 15 | ||||
-rw-r--r-- | tcl/target/stm32f4x.cfg | 63 |
3 files changed, 89 insertions, 0 deletions
diff --git a/tcl/board/stm3241g_eval.cfg b/tcl/board/stm3241g_eval.cfg new file mode 100644 index 0000000..5f1c449 --- /dev/null +++ b/tcl/board/stm3241g_eval.cfg @@ -0,0 +1,11 @@ +# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6 +# (1024KB) chip. +# http://www.st.com/internet/evalboard/product/252216.jsp + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F417IGH6 + +source [find target/stm32f4x.cfg] diff --git a/tcl/board/stm3241g_eval_stlink.cfg b/tcl/board/stm3241g_eval_stlink.cfg new file mode 100644 index 0000000..d17cdd9 --- /dev/null +++ b/tcl/board/stm3241g_eval_stlink.cfg @@ -0,0 +1,15 @@ +# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6 +# (1024KB) chip. +# http://www.st.com/internet/evalboard/product/252216.jsp +# +# This is for using the onboard STLINK/V2 + +source [find interface/stlink-v2.cfg] + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F417IGH6 + +source [find target/stm32f4x_stlink.cfg] diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg new file mode 100644 index 0000000..16beaa4 --- /dev/null +++ b/tcl/target/stm32f4x.cfg @@ -0,0 +1,63 @@ +# script for stm32f4x family + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f4x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter_khz 1000 + +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0090 + # Section 32.6.2 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0090 + # Section 32.6.3 + set _BSTAPID 0x06413041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq |