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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-12-01 01:09:10 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-12-01 01:10:19 -0800
commita65e75ea34153a8d0a0fe0b07497ad75c5726ab6 (patch)
treea9a73901dc9f6bf6e05171c616729c6b992e26cb /tcl
parent48edd58c3941c562a5a7ea78432a28e72108bbe4 (diff)
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Tcl and doc: update to match new 'arm mcr ...' etc
Make them match the C code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'tcl')
-rw-r--r--tcl/board/csb732.cfg6
-rw-r--r--tcl/board/dm355evm.cfg2
-rw-r--r--tcl/board/openrd.cfg2
-rw-r--r--tcl/board/sheevaplug.cfg2
-rw-r--r--tcl/target/c100helper.tcl8
-rw-r--r--tcl/target/imx.cfg2
6 files changed, 11 insertions, 11 deletions
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 9022faf..cad38e2 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -19,13 +19,13 @@ proc csb732_init { } {
# We assume the interpreter latency is enough.
# Allow access to all coprocessors
- mcr 15 0 15 1 0 0x2001
+ arm mcr 15 0 15 1 0 0x2001
# Disable MMU, caches, write buffer
- mcr 15 0 1 0 0 0x78
+ arm mcr 15 0 1 0 0 0x78
# Grant manager access to all domains
- mcr 15 0 3 0 0 0xFFFFFFFF
+ arm mcr 15 0 3 0 0 0xFFFFFFFF
# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 2c8bea8..db47b8d 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -182,7 +182,7 @@ proc dm355evm_init {} {
########################
# turn on icache - set I bit in cp15 register c1
- mcr 15 0 0 1 0 0x00051078
+ arm mcr 15 0 0 1 0 0x00051078
}
# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index 12cc79e..6371eff 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -29,7 +29,7 @@ proc openrd_init { } {
jtag_reset 0 0
wait_halt
- mcr 15 0 0 1 0 0x00052078
+ arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x37543000 # Dunit Control Low Register
diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index 9267eb9..b843213 100644
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -29,7 +29,7 @@ proc sheevaplug_init { } {
jtag_reset 0 0
wait_halt
- mcr 15 0 0 1 0 0x00052078
+ arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 # Dunit Control Low Register
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index 54fe07f..9658871 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -436,22 +436,22 @@ proc initC100 {} {
# */
# mov r0, #0
# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr 15 0 7 7 0 0x0
+ arm mcr 15 0 7 7 0 0x0
# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
- mcr 15 0 8 7 0 0x0
+ arm mcr 15 0 8 7 0 0x0
# /*
# * disable MMU stuff and caches
# */
# mrc p15, 0, r0, c1, c0, 0
- mrc 15 0 1 0 0
+ arm mrc 15 0 1 0 0
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
# orr r0, r0, #0x00400000 @ set bit 22 (U)
# mcr p15, 0, r0, c1, c0, 0
- mcr 15 0 1 0 0 0x401002
+ arm mcr 15 0 1 0 0 0x401002
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
# APB init
# // Setting APB Bus Wait states to 1, set post write
diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
index bfcc652..547ec56 100644
--- a/tcl/target/imx.cfg
+++ b/tcl/target/imx.cfg
@@ -10,7 +10,7 @@ proc setc15 {regs value} {
echo [format "set p15 0x%04x, 0x%08x" $regs $value]
- mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
+ arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
}