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| author | Marek Vasut <marek.vasut@gmail.com> | 2018-10-05 22:48:04 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-05-20 11:16:54 +0100 |
| commit | 82e3a0e7cfa596e1b33e924036c82ab652b51619 (patch) | |
| tree | 7b3e245e1e3923ea21204128b5b05698a1664d7c /tcl | |
| parent | 5b053ffd438714bbc0b002aaa5f0f0634a0f3fe2 (diff) | |
| download | riscv-openocd-82e3a0e7cfa596e1b33e924036c82ab652b51619.zip riscv-openocd-82e3a0e7cfa596e1b33e924036c82ab652b51619.tar.gz riscv-openocd-82e3a0e7cfa596e1b33e924036c82ab652b51619.tar.bz2 | |
tcl/target: Add Renesas RZ/A1H target
Add configuration for the Renesas RZ/A1H target.
This is an SoC with one Cortex A9 ARMv7a core and
up to 10 MiB of on-SoC SRAM.
Change-Id: I20fd54b385fe1ba1cc325451c3fdfa3a835d4884
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5141
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/renesas_r7s72100.cfg | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tcl/target/renesas_r7s72100.cfg b/tcl/target/renesas_r7s72100.cfg new file mode 100644 index 0000000..f9466fc --- /dev/null +++ b/tcl/target/renesas_r7s72100.cfg @@ -0,0 +1,25 @@ +# Renesas R-Car RZ/A1H +# https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME r7s72100 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID + +# Configuring only one core using DAP. +# Base addresses of cores: +# core 0 - 0x80030000 +set _TARGETNAME $_CHIPNAME.ca9 +dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu +target create ${_TARGETNAME} cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x80030000 + +targets ${_TARGETNAME} |