Merge commit 'adcc8ef87bc1ed47c95f1f2d23072b2b916e1555' into en-sc/from_upstream

Change-Id: I6a718561985acf398ee47cec95c6ee6e24b9c9b7

7 files changed, 455 insertions, 0 deletions

diff --git a/tcl/board/ti_j722sevm.cfg b/tcl/board/ti_j722sevm.cfg
new file mode 100644
index 0000000..6a5c2d9
--- /dev/null
+++ b/tcl/board/ti_j722sevm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Texas Instruments EVM-J722S: https://www.ti.com/lit/zip/sprr495
+#
+
+# J722S EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j722s
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/tcl/target/geehy/apm32f0x.cfg b/tcl/target/geehy/apm32f0x.cfg
new file mode 100644
index 0000000..502c092
--- /dev/null
+++ b/tcl/target/geehy/apm32f0x.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F0x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F0x devices support SWD transport only.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f0x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 1 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/tcl/target/geehy/apm32f1x.cfg b/tcl/target/geehy/apm32f1x.cfg
new file mode 100644
index 0000000..dc42e06
--- /dev/null
+++ b/tcl/target/geehy/apm32f1x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F1x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F1x devices support JTAG and SWD transport.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f1x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/tcl/target/geehy/apm32f4x.cfg b/tcl/target/geehy/apm32f4x.cfg
new file mode 100644
index 0000000..3ed58d1
--- /dev/null
+++ b/tcl/target/geehy/apm32f4x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F4x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F4x devices support JTAG and SWD transport.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f4x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+     set _CPUTAPID 0x4ba00477
+   } else {
+     set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if { [using_jtag] } {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}
diff --git a/tcl/target/marvell/cn9130.cfg b/tcl/target/marvell/cn9130.cfg
new file mode 100644
index 0000000..23e472f
--- /dev/null
+++ b/tcl/target/marvell/cn9130.cfg
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# cn9130 -- support for the Marvell Octeon TX2 / CN9130 CPU family
+#
+# henrik.nordstorm@addiva.se, Nov 2023
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME cn9130
+}
+
+if { [info exists MASTERTAPID] } {
+   set _MASTERTAPID $MASTERTAPID
+} else {
+   set _MASTERTAPID 0x07025357
+}
+
+if { [info exists APTAPID] } {
+   set _APTAPID $APTAPID
+} else {
+   set _APTAPID 0x4ba00477
+}
+
+if { [info exists SBTAPID] } {
+   set _SBTAPID $SBTAPID
+} else {
+   set _SBTAPID 0x4ba00477
+}
+
+if { [info exists CORES] } {
+   set _CORES $CORES
+} else {
+   set _CORES 4
+}
+
+# CTI base address should be possible to read from the CoreSight
+# ROM table like how the DBG base address is when not specified.
+if { [info exists CTIBASE] } {
+   set _CTIBASE $CTIBASE
+} else {
+   set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+}
+
+# CN9130 is a multi-die chip and has a multi level hierarchical
+# JTAG TAP, where all the DAPs are disabled at reset, requiring
+# both configuration to enable access to the chip DAPs, and a
+# vendor specific bypass IR instruction to access the slave TAPs
+# via the master TAP. In addition there is a number of sample
+# bits that should be ignored.
+#
+# The default BYPASS instruction in the master TAP bypasses the
+# whole chip and not only the master TAP. And similarly on
+# IDCODE the master TAP only responds with it's own ID and
+# bypasses the other TAPs on the chip, while OpenOCD expects
+# ID from all enabled TAPs in the chain.
+
+# Bootstrap with the default boundary scan oriented TAP configuration
+# where the master,ap,sb TAPs are seen as one big fat TAP, which matches
+# what OpenOCD expects from IDCODE and BYPASS.
+
+jtag newtap $_CHIPNAME bs  -irlen 19 -enable -expected-id $_MASTERTAPID
+
+# Declare the full JTAG chain, but in disabled state during setup
+
+jtag newtap $_CHIPNAME sample4 -irlen 1 -disable
+jtag newtap $_CHIPNAME sample3 -irlen 1 -disable
+jtag newtap $_CHIPNAME sample2 -irlen 1 -disable
+jtag newtap $_CHIPNAME ap.cpu  -irlen 4 -disable -expected-id $_APTAPID
+jtag newtap $_CHIPNAME ap      -irlen 5 -disable
+jtag newtap $_CHIPNAME sample1 -irlen 1 -disable
+jtag newtap $_CHIPNAME sb.cpu  -irlen 4 -disable -expected-id $_SBTAPID
+jtag newtap $_CHIPNAME sb      -irlen 5 -disable
+jtag newtap $_CHIPNAME master  -irlen 5 -disable -ir-bypass 0x11 -expected-id $_MASTERTAPID
+
+# Once the iniial IDCODE scan has completed switch to more detailed
+# scan chain giving access to the individual chip TAPs.
+
+jtag configure $_CHIPNAME.bs -event setup "cn9130_enable_full_chain $_CHIPNAME"
+
+proc cn9130_enable_full_chain { _CHIPNAME } {
+   # Switch to detailed TAP declaration
+   jtag tapdisable $_CHIPNAME.bs
+   jtag tapenable $_CHIPNAME.master
+   jtag tapenable $_CHIPNAME.sb
+   jtag tapenable $_CHIPNAME.sample1
+   jtag tapenable $_CHIPNAME.ap
+   jtag tapenable $_CHIPNAME.sample2
+   jtag tapenable $_CHIPNAME.sample3
+   jtag tapenable $_CHIPNAME.sample4
+}
+
+# AP & SB TAPs have a config register to enable/disable access to
+# the auxilary DAP TAP. Default off which hides the DAP TAP from
+# the scan chain.
+proc cn9130_dap_config { chip tap state } {
+   irscan $chip.$tap 0x12
+   drscan $chip.$tap 32 $state
+}
+
+jtag configure $_CHIPNAME.bs -event tap-disable ""
+jtag configure $_CHIPNAME.bs -event tap-enable ""
+jtag configure $_CHIPNAME.sample4 -event tap-enable ""
+jtag configure $_CHIPNAME.sample3 -event tap-enable ""
+jtag configure $_CHIPNAME.sample2 -event tap-enable ""
+jtag configure $_CHIPNAME.ap.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME ap 0"
+jtag configure cn9130.ap.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME ap 1"
+jtag configure $_CHIPNAME.ap -event tap-enable ""
+jtag configure $_CHIPNAME.sample1 -event tap-enable ""
+jtag configure $_CHIPNAME.sb.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME sb 0"
+jtag configure cn9130.sb.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME sb 1"
+jtag configure $_CHIPNAME.sb -event tap-enable ""
+jtag configure $_CHIPNAME.master -event tap-enable ""
+
+dap create $_CHIPNAME.ap.dap -chain-position $_CHIPNAME.ap.cpu
+
+# Main bus
+target create $_CHIPNAME.ap.axi mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 0
+
+# Periperials bus
+target create $_CHIPNAME.ap.apb mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 1
+
+# MSS bus
+target create $_CHIPNAME.ap.ahb mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 2
+
+# AP A72 CPU cores
+set _smp_command ""
+for { set _core 0 } { $_core < $_CORES } { incr _core 1 } {
+   cti create $_CHIPNAME.ap.cti.$_core \
+      -dap $_CHIPNAME.ap.dap \
+      -baseaddr [ lindex $_CTIBASE $_core ]  \
+      -ap-num 1
+
+   if { $_core == 0 } {
+      target create $_CHIPNAME.ap.a72.$_core aarch64 \
+         -dap $_CHIPNAME.ap.dap \
+         -ap-num 1 \
+         -cti $_CHIPNAME.ap.cti.$_core \
+         -coreid $_core \
+         -rtos hwthread
+      set _smp_command "target smp $_CHIPNAME.ap.a72.$_core"
+   } else {
+      # Defer non-boot cores. Held hard in reset until
+      # SMP is activated.
+      target create $_CHIPNAME.ap.a72.$_core aarch64 \
+         -dap $_CHIPNAME.ap.dap \
+         -ap-num 1 \
+         -cti $_CHIPNAME.ap.cti.$_core \
+         -coreid $_core \
+         -defer-examine
+      set _smp_command "$_smp_command $_CHIPNAME.ap.a72.$_core"
+   }
+
+}
+
+# Set up the A72 cluster as SMP
+# Note: Only the boot core is active by default. The other core DAPs can
+# be enabled by arp_examine after they have been released from hard reset.
+eval $_smp_command
+
+# AP MSS M3 CPU core. Defer as it is held in reset until firmware is loaded.
+target create $_CHIPNAME.ap.mss cortex_m -dap $_CHIPNAME.ap.dap -ap-num 2 -defer-examine
+
+# Why is this needed? reset fails with "Debug regions are unpowered" otherwise
+$_CHIPNAME.ap.axi configure -event examine-start "dap init"
+
+# Automate enabling the AP A72 DAP once the full scan chain is enabled
+proc cn9130_ap_setup { _CHIPNAME } {
+   jtag tapenable $_CHIPNAME.ap.cpu
+   targets $_CHIPNAME.ap.a72.0
+}
+jtag configure $_CHIPNAME.ap -event setup "cn9130_ap_setup $_CHIPNAME"
diff --git a/tcl/target/s32k.cfg b/tcl/target/s32k.cfg
new file mode 100644
index 0000000..3ff3239
--- /dev/null
+++ b/tcl/target/s32k.cfg
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Freescale S32K devices
+# Similar to Kinetis Kx series devices.
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME s32k
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x0995001d
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.pflash
+flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME -s32k
+kinetis create_banks
+
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo " Expect problems connecting to a blank device without boot ROM."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} else {
+   # Detect secured MCU or boot lock-up in RESET/WDOG loop
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+   # During RESET/WDOG loop the target is sometimes falsely examined
+   $_TARGETNAME configure -event examine-end {
+      kinetis mdm check_security
+   }
+
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 23825b8..ebea821 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -24,6 +24,8 @@
 #  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
 # * J721S2: https://www.ti.com/lit/pdf/spruj28
 #  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
+# * J722S: https://www.ti.com/lit/zip/sprujb3
+#  Has 4 ARMV8 Cores and 3 R5 Cores
 # * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
 #  Has 8 ARMV8 Cores and 8 R5 Cores
 #
@@ -185,6 +187,7 @@ switch $_soc {
 		set _dmem_emu_base_address_map_to 0x1d500000
 		set _dmem_emu_ap_list 1
 	}
+	j722s -
 	am62p -
 	am62a7 {
 		set _K3_DAP_TAPID 0x0bb8d02f
@@ -211,6 +214,14 @@ switch $_soc {
 			set _K3_DAP_TAPID 0x0bb9d02f
 			set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
 		}
+		# Overrides for j722s
+		if { "$_soc" == "j722s" } {
+			set _K3_DAP_TAPID 0x0bba002f
+			set _r5_cores 3
+			set R5_NAMES {wkup0_r5.0 main0_r5.0 mcu0_r5.0}
+			set R5_DBGBASE {0x9d410000 0x9d510000 0x9d810000}
+			set R5_CTIBASE {0x9d418000 0x9d518000 0x9d818000}
+		}
 	}
 	j721e {
 		set _K3_DAP_TAPID 0x0bb6402f