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| author | Angus Gratton <gus@projectgus.com> | 2014-07-01 10:23:25 +1000 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2014-08-11 22:26:44 +0000 |
| commit | 6d26e3e768e3be66eb7edd43d52a039a601e03cd (patch) | |
| tree | 1ec1632f8362c21a8927d0e8f948e5a45cb5e3b9 /tcl | |
| parent | 494975747376cb5258d8d84d4304df5cad51b719 (diff) | |
| download | riscv-openocd-6d26e3e768e3be66eb7edd43d52a039a601e03cd.zip riscv-openocd-6d26e3e768e3be66eb7edd43d52a039a601e03cd.tar.gz riscv-openocd-6d26e3e768e3be66eb7edd43d52a039a601e03cd.tar.bz2 | |
nRF51822: Add workaround for PAN-16 where not all RAM blocks reliably enabled on reset
According to Nordic Semiconductor Product Anomaly Notice (document
NRF51822-PAN), item 16, some revisions of nRF51822 sometimes reset
without all RAM blocks enabled. This was noted on NRF51822-QFAA rev
CA/C0, only 8KiB of memory was accessible.
This patch turns on all RAM following a debugger induced reset
(matches specified behaviour.)
Change-Id: I4f8be4ec3d1271da7fe5bc9a084fdcb2968535bb
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2202
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/nrf51.cfg | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg index abb46fd..129060d 100644 --- a/tcl/target/nrf51.cfg +++ b/tcl/target/nrf51.cfg @@ -50,3 +50,11 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME # clock to 1Mhz should be OK # adapter_khz 1000 + +proc enable_all_ram {} { + # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks + # are reliably enabled after reset on some revisions (contrary to spec.) So after + # resetting we enable all banks via the RAMON register + mww 0x40000524 0xF +} +$_TARGETNAME configure -event reset-end { enable_all_ram } |