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| author | Jiri Kastner <cz172638@gmail.com> | 2014-05-02 14:55:36 +0200 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-04-24 14:55:30 +0100 |
| commit | 5fa41168dd144a550a7c4a4961738204198cde5d (patch) | |
| tree | abb8d5e9aa70e38602ca0f774136dd6d3c7b28b0 /tcl | |
| parent | a1719e004865fb9ca556f693fd8e5c56992bc1de (diff) | |
| download | riscv-openocd-5fa41168dd144a550a7c4a4961738204198cde5d.zip riscv-openocd-5fa41168dd144a550a7c4a4961738204198cde5d.tar.gz riscv-openocd-5fa41168dd144a550a7c4a4961738204198cde5d.tar.bz2 | |
target/ti_tms570.cfg: added several JTAG IDs for TMS570LS family
from TI datasheets for whole cortex-r4 family added JTAG IDs
TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns192
0x0B95502F
16/32-Bit RISC Flash Microcontroller, TMS5703137-EP (Rev. B)
http://www.ti.com/lit/pdf/spns230
0x0D8A002F
0x2D8A002F
0x3D8A002F
RM48L952 16- and 32-Bit RISC Flash Microcontroller (Rev. B)
http://www.ti.com/lit/pdf/spns177
0x0D8A002F
0x2D8A002F
0x3D8A002F
RM46L852 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns185
0x0B95502F
RM48Lx30 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns176
0x0B8A002F
0x2B8A002F
0x3B8A002F
RM46Lx30 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns182
0x0B95502F
RM46Lx50 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns184
0x0B95502F
TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns186
0x0B97102F
RM42L432 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns180
0x0B97102F
RM46Lx40 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/
0x0B95502F
TMS570LS12x5 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns191
0x0B95502F
RM48Lx40 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns175
0x0B8A002F
0x2B8A002F
0x3B8A002F
TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns165
0x0B8A002F
0x2B8A002F
0x3B8A002F
TMS570LS20216/20206/10216/10206/10116/10106 16/32-Bit RISC Flash Microcontroller (Rev. F)
http://www.ti.com/lit/pdf/spns141
0x0B7B302F
TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller (Rev. B)
http://www.ti.com/lit/pdf/spns164
0x0B8A002F
0x2B8A002F
0x3B8A002F
RM48Lx50 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns174
0x0B8A002F
0x2B8A002F
0x3B8A002F
TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller (Rev. B)
http://www.ti.com/lit/pdf/spns162
0x0B8A002F
0x2B8A002F
0x3B8A002F
TMS570LS12x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns190
0x0B95502F
TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns189
0x0B95502F
TMS570LS11x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns188
0x0B95502F
Change-Id: Idf53a44851e1bb4bde4a74c64b65d4411e56da7c
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Tested-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/2123
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/ti_rm4x.cfg | 1 | ||||
| -rw-r--r-- | tcl/target/ti_tms570.cfg | 22 |
2 files changed, 22 insertions, 1 deletions
diff --git a/tcl/target/ti_rm4x.cfg b/tcl/target/ti_rm4x.cfg new file mode 100644 index 0000000..85c3e81 --- /dev/null +++ b/tcl/target/ti_rm4x.cfg @@ -0,0 +1 @@ +source [find target/ti_tms570.cfg] diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg index b8f9287..582a4bf 100644 --- a/tcl/target/ti_tms570.cfg +++ b/tcl/target/ti_tms570.cfg @@ -28,8 +28,28 @@ jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME. if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } + +set _JRC_TAPID2 0x0B7B302F +set _JRC_TAPID3 0x0B95502F +set _JRC_TAPID4 0x0B97102F +set _JRC_TAPID5 0x0D8A002F +set _JRC_TAPID6 0x2B8A002F +set _JRC_TAPID7 0x2D8A002F +set _JRC_TAPID8 0x3B8A002F +set _JRC_TAPID9 0x3D8A002F + + jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ - -expected-id $_JRC_TAPID -ignore-version + -expected-id $_JRC_TAPID \ + -expected-id $_JRC_TAPID2 \ + -expected-id $_JRC_TAPID3 \ + -expected-id $_JRC_TAPID4 \ + -expected-id $_JRC_TAPID5 \ + -expected-id $_JRC_TAPID6 \ + -expected-id $_JRC_TAPID7 \ + -expected-id $_JRC_TAPID8 \ + -expected-id $_JRC_TAPID9 \ + -ignore-version jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" |