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| author | Sean Anderson <sean.anderson@seco.com> | 2022-02-11 17:43:30 -0500 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-02-26 15:29:52 +0000 |
| commit | b61eae1962f008627f4593cfda9b3431e4c3c016 (patch) | |
| tree | 07032b8202f0baa7eb268996362882a22551975d /tcl | |
| parent | d673521c39dcf82ce4c2e6d9d4dcdc7460c09fbe (diff) | |
| download | riscv-openocd-b61eae1962f008627f4593cfda9b3431e4c3c016.zip riscv-openocd-b61eae1962f008627f4593cfda9b3431e4c3c016.tar.gz riscv-openocd-b61eae1962f008627f4593cfda9b3431e4c3c016.tar.bz2 | |
cpld: altera-epm240: Increase adapter speed
According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/cpld/altera-epm240.cfg | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg index 6e10188..ece02bb 100644 --- a/tcl/cpld/altera-epm240.cfg +++ b/tcl/cpld/altera-epm240.cfg @@ -17,3 +17,7 @@ jtag newtap $_CHIPNAME tap -irlen 10 \ -expected-id 0x020a40dd \ -expected-id 0x020a50dd \ -expected-id 0x020a60dd + +# 200ns seems like a good speed +# c.f. Table 5-34: MAX II JTAG Timing Parameters +adapter speed 5000 |