From b61eae1962f008627f4593cfda9b3431e4c3c016 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Feb 2022 17:43:30 -0500 Subject: cpld: altera-epm240: Increase adapter speed According to the datasheet, the minimum clock period with Vccio1 = 1.5V (the lowest voltage supported) is 143ns, or around 6MHz. Set the default adapter speed to 5 MHz. Signed-off-by: Sean Anderson Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de Reviewed-on: https://review.openocd.org/c/openocd/+/6847 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/cpld/altera-epm240.cfg | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'tcl') diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg index 6e10188..ece02bb 100644 --- a/tcl/cpld/altera-epm240.cfg +++ b/tcl/cpld/altera-epm240.cfg @@ -17,3 +17,7 @@ jtag newtap $_CHIPNAME tap -irlen 10 \ -expected-id 0x020a40dd \ -expected-id 0x020a50dd \ -expected-id 0x020a60dd + +# 200ns seems like a good speed +# c.f. Table 5-34: MAX II JTAG Timing Parameters +adapter speed 5000 -- cgit v1.1