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| author | Omair Javaid <omair.javaid@linaro.org> | 2019-03-31 01:35:43 +0500 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-06-19 09:36:02 +0100 |
| commit | ae449bb5f964032e3fb035c49aa54b6d2a9058c5 (patch) | |
| tree | e64a506b18a904c94cdbbac4c1ca7ceb68ad2e08 /tcl/target | |
| parent | bc94ca241a5d9b1bbd0b0e79f577a27dab58ecd0 (diff) | |
| download | riscv-openocd-ae449bb5f964032e3fb035c49aa54b6d2a9058c5.zip riscv-openocd-ae449bb5f964032e3fb035c49aa54b6d2a9058c5.tar.gz riscv-openocd-ae449bb5f964032e3fb035c49aa54b6d2a9058c5.tar.bz2 | |
Configs for ARM corelink SSE-200 target and Musca A board
This patch adds configuration files for ARM CoreLink SSE-200 SoCs. Also
adds configuration file for SSE-200 based Musca A board. Flash programming
support for Musca A QSPI flash is still not functional. This configuration
will be updated once that support lands into OpenOCD.
Please refer to ARM documentation for more information about SSE-200 and
Musca A.
Change-Id: Id3783c34d6e2609d659ef91c0bf7252c39439874
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/5006
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/arm_corelink_sse200.cfg | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/tcl/target/arm_corelink_sse200.cfg b/tcl/target/arm_corelink_sse200.cfg new file mode 100644 index 0000000..ca30649 --- /dev/null +++ b/tcl/target/arm_corelink_sse200.cfg @@ -0,0 +1,71 @@ +# +# Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs. +# + +global TARGET +set TARGET $_CHIPNAME + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# +# SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB +# We will configure work area assuming 8-KB bank size in SRAM bank 1. +# Also SRAM start addresses defaults to secure mode alias. +# These values can be overridden as per board configuration +# + +global _WORKAREASIZE_CPU0 +if { [info exists WORKAREASIZE_CPU0] } { + set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0 +} else { + set _WORKAREASIZE_CPU0 0x1000 +} + +global _WORKAREAADDR_CPU0 +if { [info exists WORKAREAADDR_CPU0] } { + set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0 +} else { + set _WORKAREAADDR_CPU0 0x30008000 +} + +# +# Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200 +# Core 0 is the boot core and will always be configured. +# + +target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 + +${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0 + +${TARGET}.CPU0 cortex_m reset_config sysresetreq + +# +# Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200 +# Core 1 is optional and locked at boot until core 0 unlocks it. +# + +if { $_ENABLE_CPU1 } { + global _WORKAREASIZE_CPU1 + if { [info exists WORKAREASIZE_CPU1] } { + set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1 + } else { + set _WORKAREASIZE_CPU1 0x1000 + } + + global _WORKAREAADDR_CPU1 + if { [info exists WORKAREAADDR_CPU1] } { + set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1 + } else { + set _WORKAREAADDR_CPU1 0x30009000 + } + + target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1 + + ${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0 + + ${TARGET}.CPU1 cortex_m reset_config vectreset +} + +# Make sure the default target is the boot core +targets ${TARGET}.CPU0 |