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| author | Moritz Fischer <moritz.fischer@ettus.com> | 2017-07-05 11:48:34 -0700 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-10-27 15:02:04 +0100 |
| commit | abd78a0ff8df04cd46a68ff8a716bf1eda215af0 (patch) | |
| tree | 076e92ed005a45a266506ebd3b89b646876cd132 /tcl/target | |
| parent | cf81de70524d615aa307f94b9b326bed42d7dfc0 (diff) | |
| download | riscv-openocd-abd78a0ff8df04cd46a68ff8a716bf1eda215af0.zip riscv-openocd-abd78a0ff8df04cd46a68ff8a716bf1eda215af0.tar.gz riscv-openocd-abd78a0ff8df04cd46a68ff8a716bf1eda215af0.tar.bz2 | |
zynq_7000: Add zynqpl_program command
This allows for programming the PL part of the Xilinx Zynq 7000
Change-Id: I89e86c0f381951091f6948c46802d17d7f1f3500
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: http://openocd.zylin.com/4177
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/zynq_7000.cfg | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg index 07a6c83..1562768 100644 --- a/tcl/target/zynq_7000.cfg +++ b/tcl/target/zynq_7000.cfg @@ -27,3 +27,22 @@ adapter_khz 1000 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit" ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit" + +pld device virtex2 zynq_pl.bs 1 + +set XC7_JSHUTDOWN 0x0d +set XC7_JPROGRAM 0x0b +set XC7_JSTART 0x0c +set XC7_BYPASS 0x3f + +proc zynqpl_program {tap} { + global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS + irscan $tap $XC7_JSHUTDOWN + irscan $tap $XC7_JPROGRAM + runtest 60000 + #JSTART prevents this from working... + #irscan $tap $XC7_JSTART + runtest 2000 + irscan $tap $XC7_BYPASS + runtest 2000 +} |