Merge branch 'master' into from_upstream_histogram

Used histogram diff strategy, which was much better than the default.

Conflicts:
	doc/openocd.texi
	src/flash/nor/fespi.c
	src/jtag/drivers/libjaylink
	src/rtos/rtos.c
	src/target/riscv/batch.c
	src/target/riscv/encoding.h
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h
	src/target/target.c
	tcl/target/gd32vf103.cfg

Change-Id: I1321f62ba719419e58f93b2195f2540bd62f50d2

11 files changed, 221 insertions, 11 deletions

diff --git a/tcl/target/armada370.cfg b/tcl/target/armada370.cfg
index 3b4be9f..7165274 100644
--- a/tcl/target/armada370.cfg
+++ b/tcl/target/armada370.cfg
@@ -28,6 +28,4 @@ proc armada370_dbginit {target} {
 
 $_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME"
 
-# We need to init now, so we can run the apsel command.
-init
 dap apsel 1
diff --git a/tcl/target/em357.cfg b/tcl/target/em357.cfg
index 5720071..f39f3f4 100644
--- a/tcl/target/em357.cfg
+++ b/tcl/target/em357.cfg
@@ -52,7 +52,7 @@ if { [info exists FLASHSIZE] } {
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 if { [using_jtag] } {
-    swj_newdap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
+    jtag newtap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/eos_s3.cfg b/tcl/target/eos_s3.cfg
new file mode 100644
index 0000000..f6016fb
--- /dev/null
+++ b/tcl/target/eos_s3.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# QuickLogic EOS S3
+# https://www.quicklogic.com/products/soc/eos-s3-microcontroller/
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME eos_s3
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x80000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf -expected-id _CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# For now we use SRAM only for software upload
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter speed 4000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
diff --git a/tcl/target/nds32v5.cfg b/tcl/target/nds32v5.cfg
new file mode 100644
index 0000000..56b5fed
--- /dev/null
+++ b/tcl/target/nds32v5.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Andes Core
+#
+# http://www.andestech.com
+#
+
+set _CHIPNAME nds
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563D
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index 51d032b..bf63fd5 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -146,5 +146,5 @@ if { $_ENABLE_CM0 } {
 }
 
 if {[using_jtag]} {
-	swj_newdap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
+	jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
 }
diff --git a/tcl/target/rk3308.cfg b/tcl/target/rk3308.cfg
new file mode 100644
index 0000000..d3d409e
--- /dev/null
+++ b/tcl/target/rk3308.cfg
@@ -0,0 +1,69 @@
+# Rockchip RK3308 Target
+# https://rockchip.fr/RK3308%20datasheet%20V1.5.pdf
+# https://dl.radxa.com/rockpis/docs/hw/datasheets/Rockchip%20RK3308TRM%20V1.1%20Part1-20180810.pdf
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME rk3308
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x2ba01477
+}
+
+adapter speed 12000
+
+transport select swd
+
+# declare the one SWD tap to access the DAP
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# declare the 8 main application cores
+set _TARGETNAME $_CHIPNAME.core
+set _smp_command ""
+
+set $_TARGETNAME.base(0) 0x81010000
+set $_TARGETNAME.base(1) 0x81012000
+set $_TARGETNAME.base(2) 0x81014000
+set $_TARGETNAME.base(3) 0x81016000
+
+set $_TARGETNAME.cti(0) 0x81018000
+set $_TARGETNAME.cti(1) 0x81019000
+set $_TARGETNAME.cti(2) 0x8101a000
+set $_TARGETNAME.cti(3) 0x8101b000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+                         -dbgbase [set $_TARGETNAME.base($_core)]"
+
+    if { $_core != 0 } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        # uncomment to use hardware threads pseudo rtos
+        # set _command "$_command -rtos hwthread"
+        set _command "$_command -work-area-size 0x40000 -work-area-phys 0xfff80000 \
+                                -work-area-backup 0"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+targets ${_TARGETNAME}0
diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg
new file mode 100644
index 0000000..634e07a
--- /dev/null
+++ b/tcl/target/snps_hsdk.cfg
@@ -0,0 +1,86 @@
+#  Copyright (C) 2019,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS38.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr ($_coreid << 13)]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+# ARC HS38 core 4
+set _TARGETNAME $_CHIPNAME.cpu4
+jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+# Flush L2$.
+$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 4.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 3
+set _TARGETNAME $_CHIPNAME.cpu3
+jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 3.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 2
+set _TARGETNAME $_CHIPNAME.cpu2
+jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 2.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 1
+set _TARGETNAME $_CHIPNAME.cpu1
+jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 1.
+$_TARGETNAME arc cache l2 auto 1
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 2d92eca..43a8b02 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -70,7 +70,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5
+   jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 if {![using_hla]} {
diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg
index 3a83fd1..0470bf6 100644
--- a/tcl/target/stm32w108xx.cfg
+++ b/tcl/target/stm32w108xx.cfg
@@ -42,11 +42,11 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 if {[using_jtag]} {
  if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
-   swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
  } else {
    set _BSTAPID_1 0x169a862b
    set _BSTAPID_2 0x269a862b
-   swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
 		-expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2
  }
 }
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
index 98c9a7e..ba16fab 100644
--- a/tcl/target/stm32wlx.cfg
+++ b/tcl/target/stm32wlx.cfg
@@ -38,7 +38,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
-	swj_newdap $_CHIPNAME bs -irlen 5
+	jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/swj-dp.tcl b/tcl/target/swj-dp.tcl
index 1d274cb..3fb0263 100644
--- a/tcl/target/swj-dp.tcl
+++ b/tcl/target/swj-dp.tcl
@@ -24,11 +24,12 @@ if [catch {transport select}] {
 }
 
 proc swj_newdap {chip tag args} {
- if [using_hla] {
-     eval hla newtap $chip $tag $args
- } elseif [using_jtag] {
+ if [using_jtag] {
      eval jtag newtap $chip $tag $args
  } elseif [using_swd] {
      eval swd newdap $chip $tag $args
+ } else {
+     echo "Error: transport '[ transport select ]' not supported by swj_newdap"
+     shutdown
  }
 }