target/stm32h7x: Use AP2 to access DBGMCU when non HLA adapter is used

The STM32H7 has three access ports. The DBGMCU component is available
through AP0 at 0x5C001000 and through AP2 at 0xE00E1000. Using the
latter is preferable for early configuration because it works in all
power states and while SRST is asserted, whereas the former does not.

Change-Id: Iaf8f01d769efb6655040060a8e1e951e1f7e50ab
Signed-off-by: Christopher Head <chead@zaber.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4742
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

1 files changed, 42 insertions, 6 deletions

diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 0bfc43d..ef9e29a 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -40,8 +40,14 @@ if {[using_jtag]} {
  swj_newdap $_CHIPNAME bs -irlen 5
 }
 
+if {![using_hla]} {
+	# STM32H7 provides an APB-AP at access port 2, which allows the access to
+	# the debug and trace features on the system APB System Debug Bus (APB-D).
+	target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+}
+
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -86,24 +92,24 @@ if {![using_hla]} {
 $_TARGETNAME configure -event examine-end {
 	# Enable D3 and D1 DBG clocks
 	# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
-	mmw 0x5C001004 0x00600000 0
+	stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
 
 	# Enable debug during low power modes (uses more power)
 	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
-	mmw 0x5C001004 0x00000187 0
+	stm32h7x_dbgmcu_mmw 0x004 0x00000187 0
 
 	# Stop watchdog counters during halt
 	# DBGMCU_APB3FZ1 |= WWDG1
-	mmw 0x5C001034 0x00000040 0
+	stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
 	# DBGMCU_APB4FZ1 |= WDGLSD1
-	mmw 0x5C001054 0x00040000 0
+	stm32h7x_dbgmcu_mmw 0x054 0x00040000 0
 }
 
 $_TARGETNAME configure -event trace-config {
 	# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
 	# change this value accordingly to configure trace pins
 	# assignment
-	mmw 0x5C001004 0x00100000 0
+	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -111,3 +117,33 @@ $_TARGETNAME configure -event reset-init {
 	adapter_khz 4000
 }
 
+# like mrw, but with target selection
+proc stm32h7x_mrw {used_target reg} {
+	set value ""
+	$used_target mem2array value 32 $reg 1
+	return $value(0)
+}
+
+# like mmw, but with target selection
+proc stm32h7x_mmw {used_target reg setbits clearbits} {
+	set old [stm32h7x_mrw $used_target $reg]
+	set new [expr ($old & ~$clearbits) | $setbits]
+	$used_target mww $reg $new
+}
+
+# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
+# this procedure will use the mem_ap on AP2 whenever possible
+proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
+	# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
+	if {![using_hla]} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
+		set used_target $_CHIPNAME.ap2
+		set reg_addr [expr 0xE00E1000 + $reg_offset]
+	} {
+		set used_target [target current]
+		set reg_addr [expr 0x5C001000 + $reg_offset]
+	}
+
+	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
+}