diff options
| author | Noah Moroze <noahmoroze@gmail.com> | 2024-05-15 22:47:53 -0400 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2024-06-08 08:43:30 +0000 |
| commit | 223e3d8fe76d86f01111bbe37f83a19d719ac81a (patch) | |
| tree | c14124fb40cc3e5e0e0525890bec9a22ab9ff88f /tcl/target/c100helper.tcl | |
| parent | eecba412cd8a6d515c925d87fe53e79881305517 (diff) | |
| download | riscv-openocd-223e3d8fe76d86f01111bbe37f83a19d719ac81a.zip riscv-openocd-223e3d8fe76d86f01111bbe37f83a19d719ac81a.tar.gz riscv-openocd-223e3d8fe76d86f01111bbe37f83a19d719ac81a.tar.bz2 | |
tcl/target/c100helper: fix syntax errors
Fixes: 64d89d5ee1a5 ("tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change")
These syntax errors were caught by tclint v0.2.5
(https://github.com/nmoroze/tclint):
```
tclint tcl/target/c100helper.tcl | grep "syntax error"
```
Change-Id: I511c54353c4853560adca6b4852d48df2aade283
Signed-off-by: Noah Moroze <noahmoroze@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8280
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'tcl/target/c100helper.tcl')
| -rw-r--r-- | tcl/target/c100helper.tcl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index d1d3f25..ba0e4fe 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -176,7 +176,7 @@ proc setupAmbaClk {} { mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 } + while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX @@ -250,7 +250,7 @@ proc setupArmClk {} { mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 } + while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX |