tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.

Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

5 files changed, 16 insertions, 16 deletions

diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg
index 0233cb4..dd554ce 100644
--- a/tcl/chip/atmel/at91/at91_pmc.cfg
+++ b/tcl/chip/atmel/at91/at91_pmc.cfg
@@ -87,7 +87,7 @@ set			AT91_PMC_USBS_PLLA		[expr {0 << 0}]
 set			AT91_PMC_USBS_UPLL		[expr {1 << 0}]
 set		AT91_PMC_OHCIUSBDIV	[expr {0xF <<  8}]		;# Divider for USB OHCI Clock
 
-;# set	AT91_PMC_PCKR(n)	[expr ($AT91_PMC + 0x40 + ((n) * 4))]	;# Programmable Clock 0-N Registers
+;# set	AT91_PMC_PCKR(n)	[expr {$AT91_PMC + 0x40 + ((n) * 4)}]	;# Programmable Clock 0-N Registers
 set		AT91_PMC_CSSMCK		[expr {0x1 <<  8}]		;# CSS or Master Clock Selection
 set			AT91_PMC_CSSMCK_CSS		[expr {0 << 8}]
 set			AT91_PMC_CSSMCK_MCK		[expr {1 << 8}]
diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg
index 688cb1f..27611eb 100644
--- a/tcl/chip/atmel/at91/at91sam9_init.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_init.cfg
@@ -11,7 +11,7 @@ proc at91sam9_reset_start { } {
 	jtag_rclk 8
 	halt
 	wait_halt 10000
-	set rstc_mr_val [expr $::AT91_RSTC_KEY]
+	set rstc_mr_val $::AT91_RSTC_KEY
 	set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
 	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
 	mww $::AT91_RSTC_MR $rstc_mr_val	;# RSTC_MR : enable user reset.
@@ -24,25 +24,25 @@ proc at91sam9_reset_init { config } {
 	set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
 
 	mww $::AT91_CKGR_MOR $ckgr_mor	;# CKGR_MOR - enable main osc.
-	while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }
 
-	set pllar_val	[expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
+	set pllar_val	$::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog
 	set pllar_val	[expr {$pllar_val | $::AT91_PMC_OUT}]
 	set pllar_val	[expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
-	set pllar_val	[expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
-	set pllar_val	[expr ($pllar_val | $config(master_pll_div))]
+	set pllar_val	[expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]
+	set pllar_val	[expr {$pllar_val | $config(master_pll_div)}]
 
 	mww $::AT91_CKGR_PLLAR $pllar_val	 ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
-	while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }
 
 	;# PCK/2 = MCK Master Clock from PLLA
-	set mckr_val	[expr $::AT91_PMC_CSS_PLLA]
+	set mckr_val	$::AT91_PMC_CSS_PLLA
 	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PRES_1}]
 	set mckr_val	[expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
 	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PDIV_1}]
 
 	mww $::AT91_PMC_MCKR $mckr_val	;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
-	while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }
 
 	## switch JTAG clock to highspeed clock
 	jtag_rclk 0
@@ -50,7 +50,7 @@ proc at91sam9_reset_init { config } {
 	arm7_9 dcc_downloads enable	;# Enable faster DCC downloads
 	arm7_9 fast_memory_access enable
 
-	set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
+	set rstc_mr_val $::AT91_RSTC_KEY
 	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
 	mww $::AT91_RSTC_MR $rstc_mr_val	;# user reset enable
 
diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl
index f840b78..253b7fb 100644
--- a/tcl/chip/atmel/at91/usarts.tcl
+++ b/tcl/chip/atmel/at91/usarts.tcl
@@ -63,7 +63,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
     }
     echo [format "\tParity: %s " $s]
 
-    set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
+    set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}]
     echo [format "\tDatabits: %d" $x]
 
     set x [show_normalize_bitfield $VAL 13 12]
diff --git a/tcl/chip/st/spear/quirk_no_srst.tcl b/tcl/chip/st/spear/quirk_no_srst.tcl
index 515fb58..551df06 100644
--- a/tcl/chip/st/spear/quirk_no_srst.tcl
+++ b/tcl/chip/st/spear/quirk_no_srst.tcl
@@ -24,7 +24,7 @@ set sp_reset_mode ""
 proc sp_is_halted {} {
 	global sp_target_name
 
-	return [expr [string compare [$sp_target_name curstate] "halted" ] == 0]
+	return [expr {[string compare [$sp_target_name curstate] "halted" ] == 0}]
 }
 
 # wait for reset button to be pressed, causing CPU to get halted
diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl
index ef38841..86f2a1d 100644
--- a/tcl/chip/st/spear/spear3xx.tcl
+++ b/tcl/chip/st/spear/spear3xx.tcl
@@ -19,7 +19,7 @@ proc sp3xx_clock_default {} {
 	mww 0xfca00014 0x0ffffff8	;# set pll timeout to minimum (100us ?!?)
 
 	# DDRCORE disable to change frequency
-	set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
+	set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]
 	mww 0xfca8002c $val
 	mww 0xfca8002c $val ;# Yes, write twice!
 
@@ -29,7 +29,7 @@ proc sp3xx_clock_default {} {
 	mww 0xfca80008 0x00001c0e	;# enable
 	mww 0xfca80008 0x00001c06	;# strobe
 	mww 0xfca80008 0x00001c0e
-	while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
+	while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }
 
 	# programming PLL2
 	mww 0xfca80018 0xa600010c	;# M=166, P=1, N=12
@@ -37,13 +37,13 @@ proc sp3xx_clock_default {} {
 	mww 0xfca80014 0x00001c0e	;# enable
 	mww 0xfca80014 0x00001c06	;# strobe
 	mww 0xfca80014 0x00001c0e
-	while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
+	while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }
 
 	mww 0xfca80028 0x00000082	;# enable plltimeen
 	mww 0xfca80024 0x00000511	;# set hclkdiv="/2" & pclkdiv="/2"
 
 	mww 0xfca00000 0x00000004	;# setting SYSCTL to NORMAL mode
-	while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
+	while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }
 
 	# Select source of DDR clock
 	#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1