tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.

Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
 #!/usr/bin/perl -Wpi

 my $re_sym = qr{[a-z_][a-z0-9_]*}i;
 my $re_var = qr{(?:\$|\$::)$re_sym};
 my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
 my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
 my $re_op = qr{<<|>>|[+\-*/&|]};
 my $re_expr = qr{(
     (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
     \s*$re_op\s*
     (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
 )}x;

 # [expr [dict get $regsC100 SYM] + HEXNUM]
 s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;

 # [ expr (EXPR) ]
 # [ expr EXPR ]
 # note: $re_expr captures '$3'
 s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
 s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

11 files changed, 258 insertions, 258 deletions

diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
index 8395ba3..8a371e0 100644
--- a/tcl/board/at91cap7a-stk-sdram.cfg
+++ b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -38,7 +38,7 @@ proc peek32 {address} {
 
 # Wait for an expression to be true with a timeout
 proc wait_state {expression} {
-	for {set i 0} {$i < 1000} {set i [expr $i + 1]} {
+	for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
 		if {[uplevel 1 $expression] == 0} {
 			return
 		}
diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg
index 3963e93..d6e8c2d 100644
--- a/tcl/board/at91sam9261-ek.cfg
+++ b/tcl/board/at91sam9261-ek.cfg
@@ -30,29 +30,29 @@ proc at91sam9261ek_reset_init { } {
 	;# set master_pll_mul	13
 
 	set val	[expr $::AT91_WDT_WDV]			;# Counter Value
-	set val	[expr ($val | $::AT91_WDT_WDDIS)]	;# Watchdog Disable
-	set val	[expr ($val | $::AT91_WDT_WDD)]		;# Delta Value
-	set val	[expr ($val | $::AT91_WDT_WDDBGHLT)]	;# Debug Halt
-	set val	[expr ($val | $::AT91_WDT_WDIDLEHLT)]	;# Idle Halt
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]	;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]		;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
 
 	set config(wdt_mr_val) $val
 
 	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
 	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBICSA
-	set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)]
+	set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
 
 	;# SDRAMC_CR - Configuration register
 	set val [expr $::AT91_SDRAMC_NC_9]
-	set val [expr ($val | $::AT91_SDRAMC_NR_13)]
-	set val [expr ($val | $::AT91_SDRAMC_NB_4)]
-	set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
-	set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
-	set val [expr ($val | (2 <<  8))]		;# Write Recovery Delay
-	set val [expr ($val | (7 << 12))]		;# Row Cycle Delay
-	set val [expr ($val | (3 << 16))]		;# Row Precharge Delay
-	set val [expr ($val | (2 << 20))]		;# Row to Column Delay
-	set val [expr ($val | (5 << 24))]		;# Active to Precharge Delay
-	set val [expr ($val | (8 << 28))]		;# Exit Self Refresh to Active Delay
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (2 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (3 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (8 << 28)}]		;# Exit Self Refresh to Active Delay
 
 	set config(sdram_cr_val) $val
 
diff --git a/tcl/board/at91sam9263-ek.cfg b/tcl/board/at91sam9263-ek.cfg
index 645b1a7..b88efa9 100644
--- a/tcl/board/at91sam9263-ek.cfg
+++ b/tcl/board/at91sam9263-ek.cfg
@@ -25,10 +25,10 @@ proc at91sam9263ek_reset_init { } {
 	set config(master_pll_mul)	171
 
 	set val	[expr $::AT91_WDT_WDV]			;# Counter Value
-	set val	[expr ($val | $::AT91_WDT_WDDIS)]	;# Watchdog Disable
-	set val	[expr ($val | $::AT91_WDT_WDD)]		;# Delta Value
-	set val	[expr ($val | $::AT91_WDT_WDDBGHLT)]	;# Debug Halt
-	set val	[expr ($val | $::AT91_WDT_WDIDLEHLT)]	;# Idle Halt
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]	;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]		;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
 
 	set config(wdt_mr_val) $val
 
@@ -37,22 +37,22 @@ proc at91sam9263ek_reset_init { } {
 	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBI0CSA
 
 	set val	[expr $::AT91_MATRIX_EBI0_DBPUC]
-	set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
-	set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
+	set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]
+	set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]
 	set config(matrix_ebicsa_val) $val
 
 	;# SDRAMC_CR - Configuration register
 	set val [expr $::AT91_SDRAMC_NC_9]
-	set val [expr ($val | $::AT91_SDRAMC_NR_13)]
-	set val [expr ($val | $::AT91_SDRAMC_NB_4)]
-	set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
-	set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
-	set val [expr ($val | (1 <<  8))]		;# Write Recovery Delay
-	set val [expr ($val | (7 << 12))]		;# Row Cycle Delay
-	set val [expr ($val | (2 << 16))]		;# Row Precharge Delay
-	set val [expr ($val | (2 << 20))]		;# Row to Column Delay
-	set val [expr ($val | (5 << 24))]		;# Active to Precharge Delay
-	set val [expr ($val | (1 << 28))]		;# Exit Self Refresh to Active Delay
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (1 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (2 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (1 << 28)}]		;# Exit Self Refresh to Active Delay
 
 	set config(sdram_cr_val) $val
 
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 0c971e9..1e35b68 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -80,7 +80,7 @@ proc dm355evm_init {} {
 
 	# VTPIOCR impedance calibration
 	set addr [dict get $dm355 sysbase]
-	set addr [expr $addr + 0x70]
+	set addr [expr {$addr + 0x70}]
 
 	# clear CLR, LOCK, PWRDN; wait a clock; set CLR
 	mmw $addr 0 0x20c0
@@ -108,24 +108,24 @@ proc dm355evm_init {} {
 	set addr [dict get $dm355 ddr_emif]
 
 	# DDRPHYCR1
-	mww [expr $addr + 0xe4] 0x50006404
+	mww [expr {$addr + 0xe4}] 0x50006404
 
 	# PBBPR -- burst priority
-	mww [expr $addr + 0x20] 0xfe
+	mww [expr {$addr + 0x20}] 0xfe
 
 	# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
-	mmw [expr $addr + 0x08] 0x00800000 0
-	mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
+	mmw [expr {$addr + 0x08}] 0x00800000 0
+	mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
 
 	# SDTIMR0, SDTIMR1
-	mww [expr $addr + 0x10] 0x2a923249
-	mww [expr $addr + 0x14] 0x4c17c763
+	mww [expr {$addr + 0x10}] 0x2a923249
+	mww [expr {$addr + 0x14}] 0x4c17c763
 
 	# SDCR -- relock SDTIM*
-	mmw [expr $addr + 0x08] 0 0x00008000
+	mmw [expr {$addr + 0x08}] 0 0x00008000
 
 	# SDRCR -- refresh rate (171 MHz * 7.8usec)
-	mww [expr $addr + 0x0c] 1336
+	mww [expr {$addr + 0x0c}] 1336
 
 	########################
 	# ASYNC EMIF
@@ -138,13 +138,13 @@ proc dm355evm_init {} {
 	#set nand_timings 0x0400008c
 
 	# AWCCR
-	mww [expr $addr + 0x04] 0xff
+	mww [expr {$addr + 0x04}] 0xff
 	# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
-	mww [expr $addr + 0x10] $nand_timings
+	mww [expr {$addr + 0x10}] $nand_timings
 	# CS1 == dm9000 Ethernet
-	mww [expr $addr + 0x14] 0x00a00505
+	mww [expr {$addr + 0x14}] 0x00a00505
 	# NANDFCR -- only CS0 has NAND
-	mww [expr $addr + 0x60] 0x01
+	mww [expr {$addr + 0x60}] 0x01
 
 	# default: both chipselects to the NAND socket are used
 	nand probe 0
@@ -156,27 +156,27 @@ proc dm355evm_init {} {
 	set addr [dict get $dm355 uart0]
 
 	# PWREMU_MGNT -- rx + tx in reset
-	mww [expr $addr + 0x30] 0
+	mww [expr {$addr + 0x30}] 0
 
 	# DLL, DLH -- 115200 baud
-	mwb [expr $addr + 0x20] 0x0d
-	mwb [expr $addr + 0x24] 0x00
+	mwb [expr {$addr + 0x20}] 0x0d
+	mwb [expr {$addr + 0x24}] 0x00
 
 	# FCR - clear and disable FIFOs
-	mwb [expr $addr + 0x08] 0x07
-	mwb [expr $addr + 0x08] 0x00
+	mwb [expr {$addr + 0x08}] 0x07
+	mwb [expr {$addr + 0x08}] 0x00
 
 	# IER - disable IRQs
-	mwb [expr $addr + 0x04] 0x00
+	mwb [expr {$addr + 0x04}] 0x00
 
 	# LCR - 8-N-1
-	mwb [expr $addr + 0x0c] 0x03
+	mwb [expr {$addr + 0x0c}] 0x03
 
 	# MCR - no flow control or loopback
-	mwb [expr $addr + 0x10] 0x00
+	mwb [expr {$addr + 0x10}] 0x00
 
 	# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
-	mww [expr $addr + 0x30] 0xe001
+	mww [expr {$addr + 0x30}] 0xe001
 
 
 	########################
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg
index 3b29dd8..8c7f8c0 100644
--- a/tcl/board/dm365evm.cfg
+++ b/tcl/board/dm365evm.cfg
@@ -56,10 +56,10 @@ if { $CS0 == "NAND" } {
 		#set nand_timings 0x0400008c
 
 		# CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
-		mww [expr $a_emif + 0x10] $nand_timings
+		mww [expr {$a_emif + 0x10}] $nand_timings
 
 		# NANDFCR -- CS0 has NAND
-		mww [expr $a_emif + 0x60] 0x01
+		mww [expr {$a_emif + 0x60}] 0x01
 	}
 	proc flashprobe {} {
 		nand probe 0
@@ -80,10 +80,10 @@ if { $CS0 == "NAND" } {
 		davinci_pinmux $dm365 2 0x00000055
 
 		# CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
-		mww [expr $a_emif + 0x10] 0x00000001
+		mww [expr {$a_emif + 0x10}] 0x00000001
 
 		# ONENANDCTRL -- CS0 has OneNAND, enable sync reads
-		mww [expr $a_emif + 0x5c] 0x0441
+		mww [expr {$a_emif + 0x5c}] 0x0441
 	}
 	proc flashprobe {} { }
 }
@@ -133,11 +133,11 @@ proc dm365evm_init {} {
 	set a_emif [dict get $dm365 a_emif]
 
 	# AWCCR
-	mww [expr $a_emif + 0x04] 0xff
+	mww [expr {$a_emif + 0x04}] 0xff
 	# CS0 == NAND or OneNAND
 	cs0_setup $a_emif
 	# CS1 == CPLD
-	mww [expr $a_emif + 0x14] 0x00a00505
+	mww [expr {$a_emif + 0x14}] 0x00a00505
 
 	# FIXME setup UART0
 
diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg
index 8ef9179..abf0a5f 100644
--- a/tcl/board/embedded-artists_lpc2478-32.cfg
+++ b/tcl/board/embedded-artists_lpc2478-32.cfg
@@ -26,7 +26,7 @@ proc init_board {} {
     global _CHIPNAME
 
     # A working area will help speeding the flash programming
-    $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
+    $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0
 
     # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
     flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg
index af98188..0a161f6 100644
--- a/tcl/board/icnova_imx53_sodimm.cfg
+++ b/tcl/board/icnova_imx53_sodimm.cfg
@@ -45,7 +45,7 @@ proc sodimm_init { } {
 
 	; # ARM errata ID #468414
 	set tR [arm mrc 15 0 1 0 1]
-	arm mcr 15 0 1 0 1 [expr $tR | (1<<5)]	; # enable L1NEON bit
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
 
 	init_l2cc
 	init_aips
@@ -79,7 +79,7 @@ proc init_l2cc { } {
 	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
 
 	; #mcr 15, 1, r0, c9, c0, 2
-	arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)]
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
 }
 
 
@@ -93,10 +93,10 @@ proc init_aips { } {
 	set VAL			0x77777777
 
 #	dap apsel 1
-	mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
-	mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
-	mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
-	mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
 #	dap apsel 0
 }
 
@@ -104,22 +104,22 @@ proc init_aips { } {
 proc init_clock { } {
 	global AIPS1_BASE_ADDR
 	global AIPS2_BASE_ADDR
-	set CCM_BASE_ADDR	[expr $AIPS1_BASE_ADDR + 0x000D4000]
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
 	set CLKCTL_CCSR         0x0C
 	set CLKCTL_CBCDR	0x14
 	set CLKCTL_CBCMR        0x18
-	set PLL1_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00080000]
-	set PLL2_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00084000]
-	set PLL3_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00088000]
-	set PLL4_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x0008C000]
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
 	set CLKCTL_CSCMR1	0x1C
 	set CLKCTL_CDHIPR	0x48
-	set PLATFORM_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x000A0000]
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
 	set CLKCTL_CSCDR1	0x24
 	set CLKCTL_CCDR		0x04
 
 	; # Switch ARM to step clock
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
 
 	return
 	echo "not returned"
@@ -127,52 +127,52 @@ proc init_clock { } {
 	setup_pll $PLL3_BASE_ADDR 400
 
 	; # Switch peripheral to PLL3
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
-	while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 
 	setup_pll $PLL2_BASE_ADDR 400
 
 	; # Switch peripheral to PLL2
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
 
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
 
 	; # change uart clk parent to pll2
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
 
 	; # make sure change is effective
-	while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 
 	setup_pll $PLL3_BASE_ADDR 216
 
 	setup_pll $PLL4_BASE_ADDR 455
 
 	; # Set the platform clock dividers
-	mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
 
-	mww [expr $CCM_BASE_ADDR + 0x10] 0
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
 
 	; # Switch ARM back to PLL 1.
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
 
 	; # make uart div=6
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
 
 	; # Restore the default values in the Gate registers
-	mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
 
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
 
 	; # for cko - for ARM div by 8
-	mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
 }
 
 
@@ -187,68 +187,68 @@ proc setup_pll { PLL_ADDR CLK } {
 	set PLL_DP_HFS_MFN	0x24
 
 	if {$CLK == 1000} {
-		set DP_OP	[expr (10 << 4) + ((1 - 1) << 0)]
-		set DP_MFD	[expr (12 - 1)]
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
 		set DP_MFN	5
 	} elseif {$CLK == 850} {
-		set DP_OP	[expr (8 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (48 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
 		set DP_MFN	41
 	} elseif {$CLK == 800} {
-		set DP_OP	[expr (8 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (3 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 700} {
-		set DP_OP	[expr (7 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (24 - 1)]
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
 		set DP_MFN	7
 	} elseif {$CLK == 600} {
-		set DP_OP	[expr (6 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (4 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 665} {
-		set DP_OP	[expr (6 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (96 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
 		set DP_MFN	89
 	} elseif {$CLK == 532} {
-		set DP_OP	[expr (5 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (24 - 1)]
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
 		set DP_MFN	13
 	} elseif {$CLK == 455} {
-		set DP_OP	[expr (8 << 4) + ((2 - 1)  << 0)]
-		set DP_MFD	[expr (48 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
 		set DP_MFN	71
 	} elseif {$CLK == 400} {
-		set DP_OP	[expr (8 << 4) + ((2 - 1)  << 0)]
-		set DP_MFD	[expr (3 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 216} {
-		set DP_OP	[expr (6 << 4) + ((3 - 1)  << 0)]
-		set DP_MFD	[expr (4 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
 		set DP_MFN	3
 	} else {
 		error "Error (setup_dll): clock not found!"
 	}
 
-	mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
-	mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
 
-	mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
 
-	mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
 
-	mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
 
-	mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
-	while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
 }
 
 
 proc CPU_2_BE_32 { L } {
-	return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)]
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
 }
 
 
diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg
index 2dce157..6c19654 100644
--- a/tcl/board/imx31pdk.cfg
+++ b/tcl/board/imx31pdk.cfg
@@ -6,7 +6,7 @@ $_TARGETNAME configure -event reset-init { imx31pdk_init }
 proc self_test {} {
 	echo "Running 100 iterations of test."
 	dump_image /ram/test 0x80000000 0x40000
-	for {set i 0} {$i < 100} {set i [expr $i+1]} {
+	for {set i 0} {$i < 100} {set i [expr {$i+1}]} {
 		echo "Iteration $i"
 		reset init
 		mww 0x80000000 0x12345678 0x10000
diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg
index b529c49..6f4964e 100644
--- a/tcl/board/imx53-m53evk.cfg
+++ b/tcl/board/imx53-m53evk.cfg
@@ -44,7 +44,7 @@ proc m53evk_init { } {
 
 	; # ARM errata ID #468414
 	set tR [arm mrc 15 0 1 0 1]
-	arm mcr 15 0 1 0 1 [expr $tR | (1<<5)]	; # enable L1NEON bit
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
 
 	init_l2cc
 	init_aips
@@ -75,7 +75,7 @@ proc init_l2cc { } {
 	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
 
 	; #mcr 15, 1, r0, c9, c0, 2
-	arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)]
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
 }
 
 
@@ -89,10 +89,10 @@ proc init_aips { } {
 	set VAL			0x77777777
 
 #	dap apsel 1
-	mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
-	mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
-	mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
-	mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
 #	dap apsel 0
 }
 
@@ -100,22 +100,22 @@ proc init_aips { } {
 proc init_clock { } {
 	global AIPS1_BASE_ADDR
 	global AIPS2_BASE_ADDR
-	set CCM_BASE_ADDR	[expr $AIPS1_BASE_ADDR + 0x000D4000]
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
 	set CLKCTL_CCSR         0x0C
 	set CLKCTL_CBCDR	0x14
 	set CLKCTL_CBCMR        0x18
-	set PLL1_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00080000]
-	set PLL2_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00084000]
-	set PLL3_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00088000]
-	set PLL4_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x0008C000]
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
 	set CLKCTL_CSCMR1	0x1C
 	set CLKCTL_CDHIPR	0x48
-	set PLATFORM_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x000A0000]
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
 	set CLKCTL_CSCDR1	0x24
 	set CLKCTL_CCDR		0x04
 
 	; # Switch ARM to step clock
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
 
 	return
 	echo "not returned"
@@ -123,52 +123,52 @@ proc init_clock { } {
 	setup_pll $PLL3_BASE_ADDR 400
 
 	; # Switch peripheral to PLL3
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
-	while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 
 	setup_pll $PLL2_BASE_ADDR 400
 
 	; # Switch peripheral to PLL2
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
 
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
 
 	; # change uart clk parent to pll2
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
 
 	; # make sure change is effective
-	while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 
 	setup_pll $PLL3_BASE_ADDR 216
 
 	setup_pll $PLL4_BASE_ADDR 455
 
 	; # Set the platform clock dividers
-	mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
 
-	mww [expr $CCM_BASE_ADDR + 0x10] 0
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
 
 	; # Switch ARM back to PLL 1.
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
 
 	; # make uart div=6
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
 
 	; # Restore the default values in the Gate registers
-	mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
 
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
 
 	; # for cko - for ARM div by 8
-	mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
 }
 
 
@@ -183,68 +183,68 @@ proc setup_pll { PLL_ADDR CLK } {
 	set PLL_DP_HFS_MFN	0x24
 
 	if {$CLK == 1000} {
-		set DP_OP	[expr (10 << 4) + ((1 - 1) << 0)]
-		set DP_MFD	[expr (12 - 1)]
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
 		set DP_MFN	5
 	} elseif {$CLK == 850} {
-		set DP_OP	[expr (8 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (48 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
 		set DP_MFN	41
 	} elseif {$CLK == 800} {
-		set DP_OP	[expr (8 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (3 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 700} {
-		set DP_OP	[expr (7 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (24 - 1)]
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
 		set DP_MFN	7
 	} elseif {$CLK == 600} {
-		set DP_OP	[expr (6 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (4 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 665} {
-		set DP_OP	[expr (6 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (96 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
 		set DP_MFN	89
 	} elseif {$CLK == 532} {
-		set DP_OP	[expr (5 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (24 - 1)]
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
 		set DP_MFN	13
 	} elseif {$CLK == 455} {
-		set DP_OP	[expr (8 << 4) + ((2 - 1)  << 0)]
-		set DP_MFD	[expr (48 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
 		set DP_MFN	71
 	} elseif {$CLK == 400} {
-		set DP_OP	[expr (8 << 4) + ((2 - 1)  << 0)]
-		set DP_MFD	[expr (3 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 216} {
-		set DP_OP	[expr (6 << 4) + ((3 - 1)  << 0)]
-		set DP_MFD	[expr (4 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
 		set DP_MFN	3
 	} else {
 		error "Error (setup_dll): clock not found!"
 	}
 
-	mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
-	mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
 
-	mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
 
-	mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
 
-	mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
 
-	mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
-	while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
 }
 
 
 proc CPU_2_BE_32 { L } {
-	return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)]
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
 }
 
 
diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index 91c2601..e1bc44d 100644
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -46,7 +46,7 @@ proc loco_init { } {
 
 	; # ARM errata ID #468414
 	set tR [arm mrc 15 0 1 0 1]
-	arm mcr 15 0 1 0 1 [expr $tR | (1<<5)]	; # enable L1NEON bit
+	arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]	; # enable L1NEON bit
 
 	init_l2cc
 	init_aips
@@ -80,7 +80,7 @@ proc init_l2cc { } {
 	; #orr r0, r0, #(1 << 22)          /* disable write allocate */
 
 	; #mcr 15, 1, r0, c9, c0, 2
-	arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)]
+	arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
 }
 
 
@@ -94,10 +94,10 @@ proc init_aips { } {
 	set VAL			0x77777777
 
 #	dap apsel 1
-	mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
-	mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
-	mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
-	mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+	mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
 #	dap apsel 0
 }
 
@@ -105,22 +105,22 @@ proc init_aips { } {
 proc init_clock { } {
 	global AIPS1_BASE_ADDR
 	global AIPS2_BASE_ADDR
-	set CCM_BASE_ADDR	[expr $AIPS1_BASE_ADDR + 0x000D4000]
+	set CCM_BASE_ADDR	[expr {$AIPS1_BASE_ADDR + 0x000D4000}]
 	set CLKCTL_CCSR         0x0C
 	set CLKCTL_CBCDR	0x14
 	set CLKCTL_CBCMR        0x18
-	set PLL1_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00080000]
-	set PLL2_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00084000]
-	set PLL3_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x00088000]
-	set PLL4_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x0008C000]
+	set PLL1_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00080000}]
+	set PLL2_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00084000}]
+	set PLL3_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x00088000}]
+	set PLL4_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x0008C000}]
 	set CLKCTL_CSCMR1	0x1C
 	set CLKCTL_CDHIPR	0x48
-	set PLATFORM_BASE_ADDR	[expr $AIPS2_BASE_ADDR + 0x000A0000]
+	set PLATFORM_BASE_ADDR	[expr {$AIPS2_BASE_ADDR + 0x000A0000}]
 	set CLKCTL_CSCDR1	0x24
 	set CLKCTL_CCDR		0x04
 
 	; # Switch ARM to step clock
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
 
 	return
 	echo "not returned"
@@ -128,52 +128,52 @@ proc init_clock { } {
 	setup_pll $PLL3_BASE_ADDR 400
 
 	; # Switch peripheral to PLL3
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
-	while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 
 	setup_pll $PLL2_BASE_ADDR 400
 
 	; # Switch peripheral to PLL2
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
 
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
 
 	; # change uart clk parent to pll2
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
 
 	; # make sure change is effective
-	while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+	while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 
 	setup_pll $PLL3_BASE_ADDR 216
 
 	setup_pll $PLL4_BASE_ADDR 455
 
 	; # Set the platform clock dividers
-	mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
+	mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
 
-	mww [expr $CCM_BASE_ADDR + 0x10] 0
+	mww [expr {$CCM_BASE_ADDR + 0x10}] 0
 
 	; # Switch ARM back to PLL 1.
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
 
 	; # make uart div=6
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
 
 	; # Restore the default values in the Gate registers
-	mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
-	mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+	mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
 
-	mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
+	mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
 
 	; # for cko - for ARM div by 8
-	mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
+	mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
 }
 
 
@@ -188,68 +188,68 @@ proc setup_pll { PLL_ADDR CLK } {
 	set PLL_DP_HFS_MFN	0x24
 
 	if {$CLK == 1000} {
-		set DP_OP	[expr (10 << 4) + ((1 - 1) << 0)]
-		set DP_MFD	[expr (12 - 1)]
+		set DP_OP	[expr {(10 << 4) + ((1 - 1) << 0)}]
+		set DP_MFD	[expr {12 - 1}]
 		set DP_MFN	5
 	} elseif {$CLK == 850} {
-		set DP_OP	[expr (8 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (48 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
 		set DP_MFN	41
 	} elseif {$CLK == 800} {
-		set DP_OP	[expr (8 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (3 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 700} {
-		set DP_OP	[expr (7 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (24 - 1)]
+		set DP_OP	[expr {(7 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
 		set DP_MFN	7
 	} elseif {$CLK == 600} {
-		set DP_OP	[expr (6 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (4 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 665} {
-		set DP_OP	[expr (6 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (96 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {96 - 1}]
 		set DP_MFN	89
 	} elseif {$CLK == 532} {
-		set DP_OP	[expr (5 << 4) + ((1 - 1)  << 0)]
-		set DP_MFD	[expr (24 - 1)]
+		set DP_OP	[expr {(5 << 4) + ((1 - 1)  << 0)}]
+		set DP_MFD	[expr {24 - 1}]
 		set DP_MFN	13
 	} elseif {$CLK == 455} {
-		set DP_OP	[expr (8 << 4) + ((2 - 1)  << 0)]
-		set DP_MFD	[expr (48 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {48 - 1}]
 		set DP_MFN	71
 	} elseif {$CLK == 400} {
-		set DP_OP	[expr (8 << 4) + ((2 - 1)  << 0)]
-		set DP_MFD	[expr (3 - 1)]
+		set DP_OP	[expr {(8 << 4) + ((2 - 1)  << 0)}]
+		set DP_MFD	[expr {3 - 1}]
 		set DP_MFN	1
 	} elseif {$CLK == 216} {
-		set DP_OP	[expr (6 << 4) + ((3 - 1)  << 0)]
-		set DP_MFD	[expr (4 - 1)]
+		set DP_OP	[expr {(6 << 4) + ((3 - 1)  << 0)}]
+		set DP_MFD	[expr {4 - 1}]
 		set DP_MFN	3
 	} else {
 		error "Error (setup_dll): clock not found!"
 	}
 
-	mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
-	mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
 
-	mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
 
-	mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
 
-	mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
-	mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+	mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
 
-	mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
-	while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
+	mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+	while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
 }
 
 
 proc CPU_2_BE_32 { L } {
-	return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)]
+	return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
 }
 
 
diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg
index 01080a0..a5e1902 100644
--- a/tcl/board/mcb1700.cfg
+++ b/tcl/board/mcb1700.cfg
@@ -55,7 +55,7 @@ $_TARGETNAME configure -event reset-init {
 	#
 	#
 	global MCB1700_CCLK
-	adapter speed [expr $MCB1700_CCLK / 8]
+	adapter speed [expr {$MCB1700_CCLK / 8}]
 
 	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
 	# "User Flash Mode" where interrupt vectors are _not_ remapped,