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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-30 05:37:32 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-30 05:37:32 +0000
commit642519649e9f8171f2c06260eb0280c8a060d4df (patch)
treee717ddf7f9cf7c5804cbe4674e47743c2023d17e /tcl/board
parente4de4251fe6e1fdefb4b10f4178bb7973248e0d2 (diff)
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michal smulski <michal.smulski@ooma.com> reset now works
git-svn-id: svn://svn.berlios.de/openocd/trunk@2778 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/board')
-rw-r--r--tcl/board/telo.cfg40
1 files changed, 23 insertions, 17 deletions
diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg
index a0643f7..29066f9 100644
--- a/tcl/board/telo.cfg
+++ b/tcl/board/telo.cfg
@@ -1,33 +1,34 @@
-source [find target/c100.cfg]
+source [find c100.cfg]
# basic register defintion for C100
-source [find target/c100regs.tcl]
+source [find c100regs.tcl]
# board-config info
-source [find target/c100config.tcl]
+source [find c100config.tcl]
# C100 helper functions
-source [find target/c100helper.tcl]
+source [find c100helper.tcl]
# Telo board & C100 support trst and srst
-# however openocd does not support
-# 1. setting srst reset pulse width
-# 2. setting delay between srst pulse and JTAG access
-# This really makes the srst useless for now.
+# Note that libftd2xx.so tries to assert srst
+# which break this script
+# use libftdi.so library instead with this script
+# make the reset asserted to
+# allow RC circuit to discharge for: [ms]
+jtag_nsrst_assert_width 100
+jtag_ntrst_assert_width 100
+# don't talk to JTAG after reset for: [ms]
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
reset_config trst_and_srst separate
+
# issue telnet: reset init
# issue gdb: monitor reset init
$_TARGETNAME configure -event reset-init {
jtag_khz 100
- # setup GPIO used as control signals for C100
- setupGPIO
- # This will allow acces to lower 8MB or NOR
- lowGPIO5
- # setup NOR size,timing,etc.
- setupNOR
- # setup internals + PLL + DDR2
- initC100
+ # this will setup Telo board
+ setupTelo
#turn up the JTAG speed
jtag_khz 3000
puts "JTAG speek now 3MHz"
@@ -38,10 +39,15 @@ $_TARGETNAME configure -event reset-deassert-post {
# Force target into ARM state.
# soft_reset_halt # not implemented on ARM11
puts "Detected SRSRT asserted on C100.CPU"
+
+}
+$_TARGETNAME configure -event reset-assert-post {
+ puts "Assering reset"
+ #sleep 10
}
-proc power_restore {} { puts "Sensed power restore. No action." }
+proc power_restore {} { puts "Sensed power restore. No action." }
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }