Introduce ARCv2 tcl config files

With this commit we add tcl files which describes
ARCv2 architecture features and configure files
for ARCv2 EMSK board.

Changes since v1:
-Moved from http://openocd.zylin.com/#/c/5332/4
 into separate commit.

Changes:
22.01.2020:
-Removed "actionpoints" handling code in
 tcl/cpu/arc/v2.tcl because this capability
 is not supported yet.

Changes:
17.03.2020:
-Update Licence headers
-Cleanup indents
-Removed "reset halt" in boards .tcl
-Updated adapter frequency commands

Changes:
15.03.2020:
-Removed "init" in the of boards .tcl

Change-Id: I51bf620abe7b8e046e1dccc861a7d963965d3a42
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5350
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>

4 files changed, 87 insertions, 0 deletions

diff --git a/tcl/board/snps_em_sk.cfg b/tcl/board/snps_em_sk.cfg
new file mode 100644
index 0000000..63c39a4
--- /dev/null
+++ b/tcl/board/snps_em_sk.cfg
@@ -0,0 +1,22 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.x
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# 5MHz seems to work good with all cores that might happen in 2.x
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v1.cfg b/tcl/board/snps_em_sk_v1.cfg
new file mode 100644
index 0000000..2e9d602
--- /dev/null
+++ b/tcl/board/snps_em_sk_v1.cfg
@@ -0,0 +1,20 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+adapter speed 10000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v2.1.cfg b/tcl/board/snps_em_sk_v2.1.cfg
new file mode 100644
index 0000000..5df8de5
--- /dev/null
+++ b/tcl/board/snps_em_sk_v2.1.cfg
@@ -0,0 +1,23 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
+# 20MHz. 7.5 MHz seems to work fine.
+adapter speed 7500
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v2.2.cfg b/tcl/board/snps_em_sk_v2.2.cfg
new file mode 100644
index 0000000..7f3708e
--- /dev/null
+++ b/tcl/board/snps_em_sk_v2.2.cfg
@@ -0,0 +1,22 @@
+#  Copyright (C) 2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.2
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]