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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-25 16:48:15 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-25 16:48:15 +0000 |
| commit | 43b38078787fd4f0753bdc3b150300d34678618a (patch) | |
| tree | fee59f1f9393f45b0516858bd8719b96e17be427 /tcl/board/topas910.cfg | |
| parent | 1c262c8826067b0d240f6db1c4eebf5514ea7475 (diff) | |
| download | riscv-openocd-43b38078787fd4f0753bdc3b150300d34678618a.zip riscv-openocd-43b38078787fd4f0753bdc3b150300d34678618a.tar.gz riscv-openocd-43b38078787fd4f0753bdc3b150300d34678618a.tar.bz2 | |
Michael Hasselberg <mh@open-engineering.de> target configuration files for Toshiba TX09 familiy
git-svn-id: svn://svn.berlios.de/openocd/trunk@2756 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/board/topas910.cfg')
| -rw-r--r-- | tcl/board/topas910.cfg | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/tcl/board/topas910.cfg b/tcl/board/topas910.cfg new file mode 100644 index 0000000..450a75b --- /dev/null +++ b/tcl/board/topas910.cfg @@ -0,0 +1,118 @@ +###################################### +# Target: Toshiba TOPAS910 -- TMPA910 Starterkit +# +###################################### + +# We add to the minimal configuration. +source [find target/tmpa910.cfg] + +###################### +# Target configuration +###################### + +#$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { topas910_init } + +proc topas910_init { } { +# Init PLL +# my settings + mww 0xf005000c 0x00000007 + mww 0xf0050010 0x00000065 + mww 0xf005000c 0x000000a7 + sleep 10 + mdw 0xf0050008 + mww 0xf0050008 0x00000002 + mww 0xf0050004 0x00000000 +# NEW: set CLKCR5 + mww 0xf0050054 0x00000040 +# + sleep 10 +# Init SDRAM +# _PMCDRV = 0x00000071; +# // +# // Initialize SDRAM timing paramater +# // +# _DMC_CAS_LATENCY = 0x00000006; +# _DMC_T_DQSS = 0x00000000; +# _DMC_T_MRD = 0x00000002; +# _DMC_T_RAS = 0x00000007; +# +# _DMC_T_RC = 0x0000000A; +# _DMC_T_RCD = 0x00000013; +# +# _DMC_T_RFC = 0x0000010A; +# +# _DMC_T_RP = 0x00000013; +# _DMC_T_RRD = 0x00000002; +# _DMC_T_WR = 0x00000002; +# _DMC_T_WTR = 0x00000001; +# _DMC_T_XP = 0x0000000A; +# _DMC_T_XSR = 0x0000000B; +# _DMC_T_ESR = 0x00000014; +# +# // +# // Configure SDRAM type parameter +# _DMC_MEMORY_CFG = 0x00008011; +# _DMC_USER_CONFIG = 0x00000011; +# // 32 bit memory interface +# +# +# _DMC_REFRESH_PRD = 0x00000A60; +# _DMC_CHIP_0_CFG = 0x000140FC; +# +# _DMC_DIRECT_CMD = 0x000C0000; +# _DMC_DIRECT_CMD = 0x00000000; +# +# _DMC_DIRECT_CMD = 0x00040000; +# _DMC_DIRECT_CMD = 0x00040000; +# _DMC_DIRECT_CMD = 0x00080031; +# // +# // Finally start SDRAM +# // +# _DMC_MEMC_CMD = MEMC_CMD_GO; +# */ + + mww 0xf0020260 0x00000071 + mww 0xf4300014 0x00000006 + mww 0xf4300018 0x00000000 + mww 0xf430001C 0x00000002 + mww 0xf4300020 0x00000007 + mww 0xf4300024 0x0000000A + mww 0xf4300028 0x00000013 + mww 0xf430002C 0x0000010A + mww 0xf4300030 0x00000013 + mww 0xf4300034 0x00000002 + mww 0xf4300038 0x00000002 + mww 0xf430003C 0x00000001 + mww 0xf4300040 0x0000000A + mww 0xf4300044 0x0000000B + mww 0xf4300048 0x00000014 + mww 0xf430000C 0x00008011 + mww 0xf4300304 0x00000011 + mww 0xf4300010 0x00000A60 + mww 0xf4300200 0x000140FC + mww 0xf4300008 0x000C0000 + mww 0xf4300008 0x00000000 + mww 0xf4300008 0x00040000 + mww 0xf4300008 0x00040000 + mww 0xf4300008 0x00080031 + mww 0xf4300004 0x00000000 + + sleep 10 +# jtag_speed 10000 + +# remap off in case of IROM boot + mww 0xf0000004 0x00000001 + +} + +# comment the following out if usinf J-Link, it soes not support DCC +arm7_9 dcc_downloads enable # Enable faster DCC downloads + + +##################### +# Flash configuration +##################### + +#flash bank cfi <base> <size> <chip width> <bus width> <target#> +flash bank cfi 0x20000000 0x2000000 2 2 0 |