diff options
| author | Antonio Borneo <borneo.antonio@gmail.com> | 2010-12-19 01:22:53 +0800 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-12-18 21:04:22 +0100 |
| commit | 30da7c67cec8b315972377b5389735ff11f6042c (patch) | |
| tree | f5735bd53edf0b43ef27c5058fdab817d2034462 /tcl/board/imx35pdk.cfg | |
| parent | af3f77a1777e4f28ec1a14122f4800ca3467e4c7 (diff) | |
| download | riscv-openocd-30da7c67cec8b315972377b5389735ff11f6042c.zip riscv-openocd-30da7c67cec8b315972377b5389735ff11f6042c.tar.gz riscv-openocd-30da7c67cec8b315972377b5389735ff11f6042c.tar.bz2 | |
TCL: fix non TCL comments
End of line comments fixed with ';' before '#'.
Added few additional 'space' to keep indentation in
multi-line comments.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/board/imx35pdk.cfg')
| -rw-r--r-- | tcl/board/imx35pdk.cfg | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg index 73fa633..b5aa752 100644 --- a/tcl/board/imx35pdk.cfg +++ b/tcl/board/imx35pdk.cfg @@ -27,8 +27,8 @@ proc imx35pdk_init { } { mww 0x53f00004 0x77777777 # clock setup - mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP - mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz. + mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP + mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz. #================================================= # WEIM config @@ -122,8 +122,8 @@ proc imx35pdk_init { } { mww 0x43FAC474 0x00000006 mww 0x43FAC478 0x00000006 mww 0x43FAC47c 0x00000006 - mww 0x43FAC480 0x00000006 # CSD0 - mww 0x43FAC484 0x00000006 # CSD1 + mww 0x43FAC480 0x00000006 ;# CSD0 + mww 0x43FAC484 0x00000006 ;# CSD1 mww 0x43FAC488 0x00000006 mww 0x43FAC48c 0x00000006 mww 0x43FAC490 0x00000006 @@ -131,12 +131,12 @@ proc imx35pdk_init { } { mww 0x43FAC498 0x00000006 mww 0x43FAC49c 0x00000006 mww 0x43FAC4A0 0x00000006 - mww 0x43FAC4A4 0x00000006 # RAS - mww 0x43FAC4A8 0x00000006 # CAS - mww 0x43FAC4Ac 0x00000006 # SDWE - mww 0x43FAC4B0 0x00000006 # SDCKE0 - mww 0x43FAC4B4 0x00000006 # SDCKE1 - mww 0x43FAC4B8 0x00000002 # SDCLK + mww 0x43FAC4A4 0x00000006 ;# RAS + mww 0x43FAC4A8 0x00000006 ;# CAS + mww 0x43FAC4Ac 0x00000006 ;# SDWE + mww 0x43FAC4B0 0x00000006 ;# SDCKE0 + mww 0x43FAC4B4 0x00000006 ;# SDCKE1 + mww 0x43FAC4B8 0x00000002 ;# SDCLK # SDQS0 through SDQS3 mww 0x43FAC4Bc 0x00000082 @@ -211,7 +211,7 @@ proc imx35pdk_init { } { # DDR2 : Load reg EMR1 -- OCD default mwb 0x82000780 0xda # DDR2 : Load reg EMR1 -- OCD exit - mwb 0x82000400 0xda # ODT disabled + mwb 0x82000400 0xda ;# ODT disabled # ESD_ESDCTL0 : select normal-operation mode # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit @@ -229,10 +229,10 @@ proc imx35pdk_init { } { # Adjust the ESDCDLY5 register #*********************************************** # Vary DQS_ABS_OFFSET5 for writes - mww 0xB8001020 0x00F48000 # this is the default value - mww 0xB8001024 0x00F48000 # this is the default value - mww 0xB8001028 0x00F48000 # this is the default value - mww 0xB800102c 0x00F48000 # this is the default value + mww 0xB8001020 0x00F48000 ;# this is the default value + mww 0xB8001024 0x00F48000 ;# this is the default value + mww 0xB8001028 0x00F48000 ;# this is the default value + mww 0xB800102c 0x00F48000 ;# this is the default value #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC) |