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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2021-08-16 15:24:52 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-05-14 08:43:51 +0000 |
| commit | fed329feec985b74961f5209c824ba3ca618eea7 (patch) | |
| tree | c74e18303512601d15de62e05dbcaca73e981880 /src/target | |
| parent | a785ca315ba5cb71317d43525321be8fb418bfd5 (diff) | |
| download | riscv-openocd-fed329feec985b74961f5209c824ba3ca618eea7.zip riscv-openocd-fed329feec985b74961f5209c824ba3ca618eea7.tar.gz riscv-openocd-fed329feec985b74961f5209c824ba3ca618eea7.tar.bz2 | |
arm_adi_v5: describe Class 0x9 Device Architecture register
Use the list of values from ARM IHI0029E to decode and print the
Device Architecture register.
Add attribute 'unused' to the function, not used yet.
Change-Id: I7b1dd204bd1db671578c588372b667e23611876c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6463
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/arm_adi_v5.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 2848671..d886a76 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -893,6 +893,55 @@ static const char *class_description[16] = { [0xF] = "CoreLink, PrimeCell or System component", }; +#define ARCH_ID(architect, archid) ( \ + (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \ + (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \ +) + +static const struct { + uint32_t arch_id; + const char *description; +} class0x9_devarch[] = { + /* keep same unsorted order as in ARM IHI0029E */ + { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" }, + { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" }, + { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" }, + { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" }, + { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" }, + { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" }, + { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" }, + { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" }, + { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" }, + { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" }, + { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" }, + { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" }, + { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" }, + { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" }, + { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" }, + { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" }, + { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" }, + { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" }, + { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" }, + { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" }, + { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" }, + { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" }, +}; + +#define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK) + +__attribute__((unused)) +static const char *class0x9_devarch_description(uint32_t devarch) +{ + if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT)) + return "not present"; + + for (unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++) + if ((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id) + return class0x9_devarch[i].description; + + return "unknown"; +} + static const struct { enum ap_type type; const char *description; |