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| author | drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2006-11-22 13:03:10 +0000 |
|---|---|---|
| committer | drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2006-11-22 13:03:10 +0000 |
| commit | e9297b40b994f071474210e7d9e224d50e25fcaf (patch) | |
| tree | c04957b7721ab6825e73fad0775677643f82fc23 /src/target | |
| parent | 03e8f264f4c66baec9b86778d3488b23e0a8c0b6 (diff) | |
| download | riscv-openocd-e9297b40b994f071474210e7d9e224d50e25fcaf.zip riscv-openocd-e9297b40b994f071474210e7d9e224d50e25fcaf.tar.gz riscv-openocd-e9297b40b994f071474210e7d9e224d50e25fcaf.tar.bz2 | |
- added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. configuration
- added support for loading .bit files into Xilinx Virtex-II devices
- added support for the Gateworks GW16012 JTAG dongle
- merged CFI fixes from XScale branch
- a few minor fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/armv4_5.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 00fb2f0..3eab033 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -285,7 +285,7 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 int num_regs = 37; reg_cache_t *cache = malloc(sizeof(reg_cache_t)); reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv4_5_core_reg_t *arch_info = malloc(sizeof(reg_t) * num_regs); + armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs); int i; cache->name = "arm v4/5 registers"; @@ -630,7 +630,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param for (i = 0; i <= 16; i++) { - DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32)); + DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]); ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1; |