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| author | Luca Ellero <lroluk@gmail.com> | 2011-02-08 05:16:54 +0000 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-02-08 09:42:43 +0100 |
| commit | d51b561b10bc516bf76ced479b73ae1c7b170cf7 (patch) | |
| tree | 7eddceff5aa8ce6e599ca7f4db91edd385caa6bb /src/target | |
| parent | 706284a8fd562d5a6e2c1f123f8cb366b7e49e7d (diff) | |
| download | riscv-openocd-d51b561b10bc516bf76ced479b73ae1c7b170cf7.zip riscv-openocd-d51b561b10bc516bf76ced479b73ae1c7b170cf7.tar.gz riscv-openocd-d51b561b10bc516bf76ced479b73ae1c7b170cf7.tar.bz2 | |
cortex_a8/a9: fix some comments
Signed-off-by: Luca Ellero <lroluk@gmail.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/cortex_a8.c | 8 | ||||
| -rw-r--r-- | src/target/cortex_a9.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 3c80923..f50b149 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -299,7 +299,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); - /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ + /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -318,7 +318,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, if (Rd < 15) { - /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */ + /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -326,7 +326,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, } else if (Rd == 15) { - /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 + /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "mov r15, r0" */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), @@ -339,7 +339,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, } else { - /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 + /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), diff --git a/src/target/cortex_a9.c b/src/target/cortex_a9.c index 0ede1d5..5850ace 100644 --- a/src/target/cortex_a9.c +++ b/src/target/cortex_a9.c @@ -299,7 +299,7 @@ static int cortex_a9_dap_write_coreregister_u32(struct target *target, if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); - /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ + /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */ retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -318,7 +318,7 @@ static int cortex_a9_dap_write_coreregister_u32(struct target *target, if (Rd < 15) { - /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */ + /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */ retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -326,7 +326,7 @@ static int cortex_a9_dap_write_coreregister_u32(struct target *target, } else if (Rd == 15) { - /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 + /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "mov r15, r0" */ retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), @@ -339,7 +339,7 @@ static int cortex_a9_dap_write_coreregister_u32(struct target *target, } else { - /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 + /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) */ retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), |