- correctly enter debug state on a "soft_reset_halt" command

- several small fixes
- retry reading from a FT2232 device on incomplete reads


git-svn-id: svn://svn.berlios.de/openocd/trunk@110 b42882b7-edfa-0310-969c-e2dbd0fdcd60

3 files changed, 60 insertions, 33 deletions

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index c298c90..7bf042a 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -656,6 +656,9 @@ int arm7_9_assert_reset(target_t *target)
 	
 	if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 	{
+		/* if the target wasn't running, there might be working areas allocated */
+		target_free_all_working_areas(target);
+		
 		/* assert SRST and TRST */
 		/* system would get ouf sync if we didn't reset test-logic, too */
 		if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
@@ -724,11 +727,44 @@ int arm7_9_deassert_reset(target_t *target)
 
 }
 
+int arm7_9_clear_halt(target_t *target)
+{
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+	
+	if (arm7_9->use_dbgrq)
+	{
+		/* program EmbeddedICE Debug Control Register to deassert DBGRQ
+		 */
+		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);	
+		embeddedice_store_reg(dbg_ctrl);
+	}
+	else
+	{
+		/* restore registers if watchpoint unit 0 was in use
+		 */
+		if (arm7_9->wp0_used)
+		{
+			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
+			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
+			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
+		}
+		/* control value always has to be restored, as it was either disabled, 
+		 * or enabled with possibly different bits
+		 */
+		embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
+	}
+	
+	return ERROR_OK;
+}
+
 int arm7_9_soft_reset_halt(struct target_s *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 	int i;
 	
 	if (target->state == TARGET_RUNNING)
@@ -743,6 +779,26 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 	}
 	target->state = TARGET_HALTED;
 	
+	/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
+	 * ensure that DBGRQ is cleared
+	 */
+	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
+	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
+	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
+	embeddedice_store_reg(dbg_ctrl);
+	
+	arm7_9_clear_halt(target);
+	
+	/* if the target is in Thumb state, change to ARM state */
+	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
+	{
+		u32 r0_thumb, pc_thumb;
+		DEBUG("target entered debug from Thumb state, changing to ARM");
+		/* Entered debug from Thumb mode */
+		armv4_5->core_state = ARMV4_5_STATE_THUMB;
+		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
+	}
+	
 	/* all register content is now invalid */
 	armv4_5_invalidate_core_regs(target);
 	
@@ -819,38 +875,6 @@ int arm7_9_halt(target_t *target)
 	return ERROR_OK;
 }
 
-int arm7_9_clear_halt(target_t *target)
-{
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
-	
-	if (arm7_9->use_dbgrq)
-	{
-		/* program EmbeddedICE Debug Control Register to deassert DBGRQ
-		 */
-		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);	
-		embeddedice_store_reg(dbg_ctrl);
-	}
-	else
-	{
-		/* restore registers if watchpoint unit 0 was in use
-		 */
-		if (arm7_9->wp0_used)
-		{
-			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
-			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
-			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
-		}
-		/* control value always has to be restored, as it was either disabled, 
-		 * or enabled with possibly different bits
-		 */
-		embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
-	}
-	
-	return ERROR_OK;
-}
-
 int arm7_9_debug_entry(target_t *target)
 {
 	int i;
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index 3da9273..a30d67a 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -167,6 +167,10 @@ int watchpoint_add(target_t *target, u32 address, u32 length, enum watchpoint_rw
 				INFO("can't add %s watchpoint, resource not available", watchpoint_rw_strings[rw]);
 				return retval;
 				break;
+			case ERROR_TARGET_NOT_HALTED:
+				INFO("can't add watchpoint while target is running");
+				return retval;
+				break;
 			default:
 				ERROR("unknown error");
 				exit(-1);
diff --git a/src/target/target.c b/src/target/target.c
index 531d632..7322888 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -904,7 +904,6 @@ int handle_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a
 				(*last_target_p)->working_areas = NULL;
 				(*last_target_p)->backup_working_area = 0;
 				
-				(*last_target_p)->endianness = TARGET_LITTLE_ENDIAN;
 				(*last_target_p)->state = TARGET_UNKNOWN;
 				(*last_target_p)->reg_cache = NULL;
 				(*last_target_p)->breakpoints = NULL;