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author | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-23 22:40:33 +0000 |
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committer | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-23 22:40:33 +0000 |
commit | 6319ea33f7369823043eaefdb72b7463e760be27 (patch) | |
tree | d91702e6b2722e9a9cedb0a92bea31491520ed65 /src/target | |
parent | 4ce93ac479c29210c4b472a16733bed2537c35f9 (diff) | |
download | riscv-openocd-6319ea33f7369823043eaefdb72b7463e760be27.zip riscv-openocd-6319ea33f7369823043eaefdb72b7463e760be27.tar.gz riscv-openocd-6319ea33f7369823043eaefdb72b7463e760be27.tar.bz2 |
- Fixes '<=' whitespace
- Replace '\(\w\)\(<=\)\(\w\)' with '\1 \2 \3'.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2368 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target')
-rw-r--r-- | src/target/arm7_9_common.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 692ab16..985b9f6 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -1428,7 +1428,7 @@ int arm7_9_debug_entry(target_t *target) if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=15; i++) + for (i=0; i <= 15; i++) { LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]); @@ -2362,7 +2362,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=last_reg; i++) + for (i=0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2545,7 +2545,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=last_reg; i++) + for (i=0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); |