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| author | Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> | 2024-06-04 18:49:42 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-04 18:49:42 +0300 |
| commit | b548653f66db7cc73bd0bdce33bc51220e509078 (patch) | |
| tree | 34bfe01e9750ea6e03f622bf78827b7812ef5b6e /src/target/riscv/riscv.h | |
| parent | 8568f9b9af5bc72569d014ae13b0d3263e4f7090 (diff) | |
| parent | 2c00a087daddbc478f2b9d691bc9706a60f0681b (diff) | |
| download | riscv-openocd-b548653f66db7cc73bd0bdce33bc51220e509078.zip riscv-openocd-b548653f66db7cc73bd0bdce33bc51220e509078.tar.gz riscv-openocd-b548653f66db7cc73bd0bdce33bc51220e509078.tar.bz2 | |
Merge pull request #1056 from aap-sc/aap-sc/no_hit_bit_status
target/riscv: fix halt reason for targets that do not support hit bit on triggers
Diffstat (limited to 'src/target/riscv/riscv.h')
| -rw-r--r-- | src/target/riscv/riscv.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 7a95af6..d3703d1 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -159,11 +159,11 @@ struct riscv_info { * >= 0: unique_id of the breakpoint/watchpoint that is using it. * Note that in RTOS mode the triggers are the same across all harts the * target controls, while otherwise only a single hart is controlled. */ - int trigger_unique_id[RISCV_MAX_HWBPS]; + int64_t trigger_unique_id[RISCV_MAX_HWBPS]; /* The unique id of the trigger that caused the most recent halt. If the * most recent halt was not caused by a trigger, then this is -1. */ - uint32_t trigger_hit; + int64_t trigger_hit; /* The number of entries in the program buffer. */ int progbuf_size; |