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authorTim Newsome <tim@sifive.com>2018-04-30 13:36:06 -0700
committerTim Newsome <tim@sifive.com>2018-04-30 13:36:06 -0700
commitb62c014bdc7a4b9a88ac6f44328c01ea4974c46a (patch)
tree0a02bae7a34dd3db3f410885b79c71d171bd9b2f /src/target/riscv/riscv.h
parent9a69c1c096a5498900c997daa17f23fbc5d7b87d (diff)
parent8956edd8aa2dbfed06c1d4fe5b6d2e26540f670b (diff)
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Merge branch 'riscv' into notice_reset
Diffstat (limited to 'src/target/riscv/riscv.h')
-rw-r--r--src/target/riscv/riscv.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index 1e6ffb9..63a3b79 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -38,8 +38,6 @@ enum riscv_halt_reason {
typedef struct {
unsigned dtm_version;
- riscv_reg_t misa;
-
struct command_context *cmd_ctx;
void *version_specific;
@@ -69,6 +67,7 @@ typedef struct {
/* It's possible that each core has a different supported ISA set. */
int xlen[RISCV_MAX_HARTS];
+ riscv_reg_t misa[RISCV_MAX_HARTS];
/* The number of triggers per hart. */
unsigned trigger_count[RISCV_MAX_HARTS];
@@ -128,6 +127,8 @@ extern int riscv_reset_timeout_sec;
extern bool riscv_use_scratch_ram;
extern uint64_t riscv_scratch_ram_address;
+extern bool riscv_prefer_sba;
+
/* Everything needs the RISC-V specific info structure, so here's a nice macro
* that provides that. */
static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
@@ -182,7 +183,7 @@ int riscv_resume_one_hart(struct target *target, int hartid);
* then the only hart. */
int riscv_step_rtos_hart(struct target *target);
-bool riscv_supports_extension(struct target *target, char letter);
+bool riscv_supports_extension(struct target *target, int hartid, char letter);
/* Returns XLEN for the given (or current) hart. */
int riscv_xlen(const struct target *target);